Abstract: There is provided a multilayer electronic component in which a short circuit between the internal electrodes, a decrease in capacitance, a decrease in breakdown voltage, and the like, may be suppressed by controlling an area fraction occupied by a region in which an intensity of brightness in a capacitance formation portion is 110% or more and 126% or less of an average value of an intensity of brightness of a cover portion.

Abstract: There is provided a multilayer electronic component in which a short circuit between the internal electrodes, a decrease in capacitance, a decrease in breakdown voltage, and the like, may be suppressed by controlling an area fraction occupied by a region in which an intensity of brightness in a capacitance formation portion is 110% or more and 126% or less of an average value of an intensity of brightness of a cover portion.

Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

Abstract: A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

Abstract: Metal wiring structures for integrated circuits include a seed layer formed on an integrated circuit substrate and a wetting layer formed on the seed layer opposite the integrated circuit substrate. A metal wiring layer is formed on the wetting layer opposite the seed layer. The seed layer and the metal wiring layer have the same crystal orientation. In a preferred embodiment, the seed layer is an aluminum layer having (111) crystal orientation and the metal wiring layer includes aluminum having (111) crystal orientation. The metal wiring layer may be aluminum or an aluminum alloy. The wetting layer preferably includes titanium.

Abstract: Wafer debonding of a bonded bulk wafer and a device wafer using a liquid jet to avoid scratching of the wafers is provided. The wafer debonder includes a wafer loader having a first stand with a flat upper surface and a second stand located above the first stand having a lower surface slanted with respect to the upper surface of the first stand at a predetermined angle. A first holder is connected to the first stand and a second holder is located on an imaginary surface extended from the lower surface of the second stand for holding the wafers. A liquid jetting nozzle is positioned adjacent the wafer loader to direct a jet of liquid at the interface between the wafers to separate the wafers.

Abstract: Wafer debonding of a bonded bulk wafer and a device wafer using a liquid jet to avoid scratching of the wafers is provided. The wafer debonder includes a wafer loader having a first stand with a flat upper surface and a second stand located above the first stand having a lower surface slanted with respect to the upper surface of the first stand at a predetermined angle. A first holder is connected to the first stand and a second holder is located on an imaginary surface extended from the lower surface of the second stand for holding the wafers. A liquid jetting nozzle is positioned adjacent the wafer loader to direct a jet of liquid at the interface between the wafers to separate the wafers.

Abstract: An apparatus for bonding semiconductor wafers firmly bonds the wafers to each other and can always lay the bonded wafers on a desired bonding plate. The bonding plates have a plurality of grooves formed on their respective surfaces to reduce the bond force between the wafers and the bonding plates of the apparatus, and to prevent the wafers from sliding off the plates due to an air cushion. An interval controlling pin projects from the surface of one of the bonding plates to reduce breakage of the wafers by maintaining an interval between the bonding plates as they are are rotated towards each other. An elastic pad portion is installed on one the bonding plates for providing an elastic force for the wafers placed on the bonding plates so that the wafers bond to each other properly when the bonding plates are further rotated towards each other.

Abstract: A SOI substrate manufacturing method which corrects the warpage in the SOI substrate by varying the thickness of a semiconductor material layer additionally formed over the bonded combination of a semiconductor substrate and supporting substrate.