Abstract: A dual-plane type flash memory device having a random program function and program operation method thereof. The flash memory device includes a first plane, a second plane, a first X-decoder, and a second X-decoder. The first plane includes first memory blocks sequentially arranged in a row direction. The second plane includes second memory blocks sequentially arranged in a row direction. The first X-decoder activates one of the first memory blocks in response to a first block address signal. The second X-decoder activates one of the second memory blocks in response to a second block address signal. The block activated by the first X-decoder of the first memory block is different from the block activated by the second X-decoder of the second memory blocks. Accordingly, during a program operation, memory blocks of two planes having different block addresses can be selected and programmed. Accordingly, the operational performance of the flash memory device can be enhanced.

Abstract: A flash memory device includes first to nth banks sharing an I/O line, a page buffer unit commonly connected to a bit line of the first to nth banks, for buffering data to be transmitted to the first to nth banks, a first X-decoder connected to a word line of the first banks, for applying a driving voltage to the word line of the first banks, a nth X-decoder connected to a word line of the nth banks, for applying a driving voltage to the word line of the nth banks, a program/erase pump for generating a program voltage/erase voltage applied to the first to nth banks, a first switch unit that switches the program voltage/erase voltage and transmits the voltage to the first banks and the first X-decoder, and a nth switch unit that switches the program voltage/erase voltage and transmits the voltage to the nth banks and the nth X-decoder.

Abstract: A flash memory device and method of controlling a program operation thereof, includes page buffers divided into a predetermined number of groups and a program operation is performed on a group basis.

Abstract: A method for operating a page buffer of a nonvolatile memory device reduces errors while transferring data between latches and shortens a copy-back programming time. The copy-back program is carried out using one among several latch circuits included in the page buffer. The method activates a first latch circuit while inactivates a second latch circuit, in a copy-back programming operation, and activates the first and second latch circuits in programming, reading, and verifying operations.

Abstract: Disclosed herein are a page buffer and a verify method of a flash memory device where the page buffer of a dual register structure includes a switch, which is driven according to a voltage level of an input terminal of a main latch, to output an erase-verify signal, and a switch, which is driven according to a voltage level of an output terminal of the main latch, to output a program-verify signal. Program-verify and erase-verify operations are performed using only the main latch. The disclosed page buffer and verify method can reduce verification time relative to devices using both a cache latch and a main latch.

Abstract: The present invention discloses a page buffer having a dual register, a semiconductor memory device having the same, and a program method thereof. A data transmission path is formed by installing switching units so that a main register as well as a cache register can be directly provided with a data. Therefore, a program operation is performed directly by using the main register in a normal program operation, and by using the cache register in a cache program operation. Accordingly, a process for transmitting the data from the cache register to the main register is omitted in the normal program operation, to reduce a transmission time (about 3 ?s). As a result, the program time can be reduced in the whole program operation. Because the process for transmitting the data from the cache register to the main register is omitted in the normal program operation, the circuit control operation can be simplified.

Abstract: The disclosed is a page buffer of a flash memory device. In accordance with the present invention, a latch is controlled through a program verification signal, a latch signal, and latch data in a page buffer during a program verification. As a result, there are many advantages. First, in the event that the program verification is performed after programming once more, a passed cell is not sensed again and maintains its value. Second, it is possible to prevent a problem caused by a sensing operation as well as a verification error due to an external factor. As a result, program operation errors can be prevented.