Abstract: A memory system or memory controller may calculate a first data size, which is the sum of sizes of data requested to be written by write requests from outside the memory system after a first reference time point, calculate a second data size, which is the sum of sizes of data updated by the write requests among data already stored in the memory device from a second reference time point, and control execution of garbage collection on data stored in the memory device based on the first data size and the second data size.

Abstract: A storage device capable of maintaining consistency of data for the same address may include a memory device including a plurality of memory blocks, a buffer memory device including a plurality of cache buffers temporarily storing data previously received from a host, and a memory controller configured to receive a write request and a write data from the host and configured to control the buffer memory device and the memory device to store a previously received data, stored in one of the plurality of cache buffers with a logical address that matches a logical address of the write data, in the memory device before the write request is processed.

Abstract: A memory system includes a memory device including a plurality of non-volatile memory cells; and a controller configured to program data input from an external device in the memory device, generate a map data item corresponding to the data, perform a compression operation on second map data when the second map data includes no empty area for the map data item. A timing of updating first map data stored in the memory device based on the second map data is determined according to whether the second map data is compressed or not.

Abstract: A memory system may include a memory device including a first memory block group and a second memory block group; and a memory controller configured to designate a first memory block of memory blocks included in the first memory block group as an open block and designate a second memory block of memory blocks included in the second memory block group as the open block, and perform a program operation on the first and second memory blocks designated as the open blocks. When the first memory block designated as the open block is changed to a closed block, the memory controller may determine whether to designate a third memory block among the memory blocks included in the first or the second memory block group as a new open block based on a number of times voltage abnormalities have occurred on a voltage supplied to the memory device.

Abstract: A data storage device includes a nonvolatile memory device which includes a first nonvolatile memory group including a plurality of first nonvolatile memories coupled to a first flash translation layer (FTL) core and a second nonvolatile memory group including a plurality of second nonvolatile memories coupled to a second FTL core, and a controller including the first FTL core configured to write first user data transmitted from the host device and second metadata related to second user data in one among the plurality of first nonvolatile memories and a common memory.

Abstract: A data storage device includes a nonvolatile memory device which includes a first nonvolatile memory group including a plurality of first nonvolatile memories coupled to a first flash translation layer (FTL) core and a second nonvolatile memory group including a plurality of second nonvolatile memories coupled to a second FTL core, and a controller including the first FTL core configured to write first user data transmitted from the host device and second metadata related to second user data in one among the plurality of first nonvolatile memories and a common memory.

Abstract: A controller that controls a memory device, the controller includes: a buffer including a plurality of segments; a host interface configured to determine a command group of a command from a host on the basis of an attribute of the command; and a buffer manager configured to allocate a free segment among the plurality of segments in response to a segment allocation request from the host interface, wherein the host interface further processes data associated with the command by using the allocated segment.

Abstract: The present technology relates to an electronic device. A memory controller controls a memory device to efficiently use a storage space of the memory device. The memory controller controlling the memory device includes a cache buffer configured to store data received from a host and output the data to the memory device, and a program mode setting component configured to determine a program mode based on a size of the data output from the cache buffer to the memory device, and output an address and a command according to the determined program mode.

Abstract: A storage device capable of maintaining consistency of data for the same address may include a memory device including a plurality of memory blocks, a buffer memory device including a plurality of cache buffers temporarily storing data previously received from a host, and a memory controller configured to receive a write request and a write data from the host and configured to control the buffer memory device and the memory device to store a previously received data, stored in one of the plurality of cache buffers with a logical address that matches a logical address of the write data, in the memory device before the write request is processed.

Abstract: A memory system includes a memory device including a plurality of non-volatile memory cells; and a controller configured to program data input from an external device in the memory device, generate a map data item corresponding to the data, perform a compression operation on second map data when the second map data includes no empty area for the map data item. A timing of updating first map data stored in the memory device based on the second map data is determined according to whether the second map data is compressed or not.

Abstract: A data storage device may include a storage and a controller for controlling the storage. The controller may include a garbage collection controller. The garbage collection controller may predict whether at least one memory block may be invalidated or not, based on a new write command with respect to a logical address having a previous write record. When the garbage collection controller predicts the invalidation of the at least one memory block, the garbage collection controller may control a garbage collection policy.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a page buffer group configured to include a plurality of page buffers respectively coupled to a plurality of memory areas through a plurality of bit lines, a row decoder configured to select a memory area, on which an operation corresponding to a command is to be performed, from among the plurality of memory areas, based on a row address included in an address, a column decoder configured to transfer data to a page buffer of the plurality of page buffers according to a column address included in the address and an address controller configured to control the row decoder and the column decoder so that the data is stored in another memory area other than the selected memory area.

Abstract: Provided is an operation method of a controller which controls a memory device including a plurality of memory blocks. The operation method may include calculating a number of extended free blocks in the memory device based on valid page counts of the respective memory blocks, when a number of substantive free blocks in the memory device is less than a first threshold value, and performing a garbage collection operation when the number of extended free blocks is less than a second threshold value.

Abstract: A memory controller may control a memory device, which includes two or more planes each including a plurality of memory blocks, which are capable of being simultaneously operated, wherein each of two or more memory blocks in different planes, among the two or more planes, stores a plurality of data chunks. The memory controller may include a data map generator configured to generate a data map indicating locations of stored valid data chunks, among the plurality of data chunks, a read sequence determinator configured to determine a read sequence in which the valid data chunks are to be read based on the data map, and a command input controller configured to provide a read command for the valid data chunks to the memory device based on the read sequence.

Abstract: A memory system include a memory device including a plurality of non-volatile memory cells, and a controller configured to determine a pattern regarding a plurality of data input/output requests, control map data to have a data structure based on the pattern, and program map information included in the map data into the memory device. A timing of programming the map information can be based on the data structure of the map data.

Abstract: The present technology relates to an electronic device. A memory controller controls a memory device to efficiently use a storage space of the memory device. The memory controller controlling the memory device includes a cache buffer configured to store data received from a host and output the data to the memory device, and a program mode setting component configured to determine a program mode based on a size of the data output from the cache buffer to the memory device, and output an address and a command according to the determined program mode.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a page buffer group configured to include a plurality of page buffers respectively coupled to a plurality of memory areas through a plurality of bit lines, a row decoder configured to select a memory area, on which an operation corresponding to a command is to be performed, from among the plurality of memory areas, based on a row address included in an address, a column decoder configured to transfer data to a page buffer of the plurality of page buffers according to a column address included in the address and an address controller configured to control the row decoder and the column decoder so that the data is stored in another memory area other than the selected memory area.

Abstract: A memory system may include a memory device including a first memory block group and a second memory block group; and a memory controller configured to designate a first memory block of memory blocks included in the first memory block group as an open block and designate a second memory block of memory blocks included in the second memory block group as the open block, and perform a program operation on the first and second memory blocks designated as the open blocks. When the first memory block designated as the open block is changed to a closed block, the memory controller may determine whether to designate a third memory block among the memory blocks included in the first or the second memory block group as a new open block based on a number of times voltage abnormalities have occurred on a voltage supplied to the memory device.

Abstract: A data storage device may include a storage and a controller for controlling the storage. The controller may include a garbage collection controller. The garbage collection controller may predict whether at least one memory block may be invalidated or not, based on a new write command with respect to a logical address having a previous write record. When the garbage collection controller predicts the invalidation of the at least one memory block, the garbage collection controller may control a garbage collection policy.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory blocks, and a memory controller configured to control the memory device and perform a garbage collection operation of securing free blocks in which data is not stored, based on a sum of a number of invalid data blocks and a number of free blocks, among the plurality of memory blocks, wherein the number of invalid data blocks is determined depending on a size of invalid data stored in the plurality of memory blocks.