Abstract: A multilayer electronic component according to an embodiment of the present disclosure includes a body including a capacitance forming portion including a dielectric layer and an internal electrode layer, and a cover portion; and an external electrode disposed on the body, wherein the cover portion includes a plurality of dummy electrode layers disposed to be spaced apart from the capacitance forming portion in the first direction, and the dummy electrode layers include dummy electrodes disposed to be spaced apart from each other in a second direction and connected to the external electrode, and a dummy electrode layer disposed in a position closest to the capacitance forming portion is disposed in a position spaced apart from the capacitance forming portion by d in the first direction, and, if a first direction average length of the dielectric layer is td, td and d satisfy td<d.

Abstract: A multilayer capacitor includes a capacitor body having first to sixth surfaces, including a plurality of first and second dielectric layers and a plurality of internal electrodes stacked; and first and second external electrodes. The internal electrode includes first and second internal electrodes, a first floating electrode disposed between the first and second internal electrodes on the first dielectric layer, and second and third floating electrodes disposed on the second dielectric layer. The second floating electrode overlaps a portion of the first internal electrode and a portion of the first floating electrode, and the third floating electrode overlaps a portion of the second internal electrode and a portion of the first floating electrode. a/L is 0.113 or more, in which L is a length of the capacitor body, and a is a distance between the first floating electrode and the first or second internal electrodes.

Abstract: A multilayer electronic component includes: a body including dielectric layers and internal electrodes alternately stacked with one of the dielectric layers interposed therebetween; and external electrodes disposed on external surfaces of the body and connected to the internal electrodes. One of the internal electrodes includes a plurality of conductive particles and conductive nanowires each of which having a shape different from a shape of the plurality of conductive particles and being connected to at least one of the plurality of conductive particles.

Abstract: A multilayer capacitor includes a capacitor body having first to sixth surfaces, including a plurality of first and second dielectric layers and a plurality of internal electrodes stacked; and first and second external electrodes. The internal electrode includes first and second internal electrodes, a first floating electrode disposed between the first and second internal electrodes on the first dielectric layer, and second and third floating electrodes disposed on the second dielectric layer. The second floating electrode overlaps a portion of the first internal electrode and a portion of the first floating electrode, and the third floating electrode overlaps a portion of the second internal electrode and a portion of the first floating electrode. a/L is 0.113 or more, in which L is a length of the capacitor body, and a is a distance between the first floating electrode and the first or second internal electrodes.

Abstract: A multilayer electronic component includes: a body including dielectric layers and internal electrodes alternately stacked with one of the dielectric layers interposed therebetween; and external electrodes disposed on external surfaces of the body and connected to the internal electrodes. One of the internal electrodes includes a plurality of conductive particles and conductive nanowires each of which having a shape different from a shape of the plurality of conductive particles and being connected to at least one of the plurality of conductive particles.

Abstract: A lead pin for a package substrate includes: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate.

Abstract: A lead pin for a package substrate includes: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate.

Abstract: Disclosed herein are a package substrate and a fabricating method thereof. The package substrate includes a substrate including at least one conductive pad, an insulation layer formed on the substrate and including an opening through which the conductive pad is exposed, a blister prevention layer formed along a top surface of the conductive pad exposed through the opening and a sidewall of the insulation layer, a metal post made of at least one alloy material and formed on the blister prevention layer, and a heat-diffusion prevention film formed on the metal post.

Abstract: There is provided a lead pin for a package substrate including: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate.

Abstract: Disclosed herein are a package substrate and a fabricating method thereof. The package substrate includes a substrate including at least one conductive pad, an insulation layer formed on the substrate and including an opening through which the conductive pad is exposed, a blister prevention layer formed along a top surface of the conductive pad exposed through the opening and a sidewall of the insulation layer, a metal post made of at least one alloy material and formed on the blister prevention layer, and a heat-diffusion prevention film formed on the metal post.

Abstract: There is provided a lead pin for a package substrate including: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate.