Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.

Abstract: A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair.

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based Self-Aligning Double Patterning (SADP) emulation, comparing the first emulation pattern with the first mask data pattern, and modifying the second mask data pattern according to results of the comparison. The method further includes performing Optical Proximity Correction (OPC) on the modified second mask data pattern, acquiring second emulation patterns, which are predicted from the second mask data pattern on which the OPC has been performed, using image-based SADP emulation, and comparing the second emulation patterns and the first mask data pattern and manufacturing a first mask layer, which corresponds to the second mask data pattern on which the OPC has been performed, according to the results of the comparison.

Abstract: Provided is a method for forming patterns of a semiconductor device. According to the method, first mask patterns may be formed on a substrate, and second mask patterns may be formed on sidewalls of each first mask pattern. Third mask patterns may fill spaces formed between adjacent second mask patterns, and the second mask patterns may be removed. A portion of the substrate may then be removed using the first and third mask patterns as etch masks.

Abstract: Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.

Abstract: Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.

Abstract: A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

Abstract: Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: Disclosed is an E-beam lithography system for synchronously irradiating surfaces of a plurality of substrates. The E-beam lithography system may include a loading unit loading and unloading substrates, an alignment chamber aligning the substrates, a transfer chamber transferring the substrates from the loading unit or chambers, a lithography chamber radiating one or more electron beams onto the substrates, and a vacuum chamber creating a vacuum in the chambers. A stage may be installed in the lithography chamber such that the substrates may be mounted on the stage and radiated with one or more electron beams.