Abstract: In a semiconductor memory device having a plurality of memory cells and a data output buffer for transferring a data signal from the memory cells to external peripheral circuits, a circuit for controlling the data output buffer, comprising a address transition detector for detecting a transition of an address signal to generate an address transition detect signal in a pulse form, a delay controller for generating a delay control signal, the delay control signal having a logic value set by a manufacturer according to whether the semiconductor memory device has a repaired memory cell, and an output enable signal generator for generating an output enable signal at a time point delayed by a time period from the generation of the address transition detect signal from the address transition detector, the time period being determined based on a logic value of the delay control signal from the delay controller, the output enable signal generator outputting the output enable signal to the data output buffer to control