Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: A power supply boosting circuit provides increased pumping efficiency by driving the gate of a transistor in a first precharge circuit with the pumped output voltage from a second precharge circuit, thereby eliminating a threshold voltage drop from the output voltage of the first precharge circuit. The pumped output voltage from the first precharge circuit is then used to precharge a pumping node in a pumping circuit, which in turn, eliminates a threshold voltage drop from the output voltage of the pumping circuit. A transistor in the second precharge circuit can likewise be driven by the pumped output voltage from the first precharge circuit, further increasing the pumping efficiency.

Abstract: A semiconductor memory device with multi-bank structure, includes multiple voltage boosting circuits or internal power supply voltage generating circuits, each of which generates a high voltage to be provided to a bank. The respective voltage boosting circuits or internal power supply voltage generating circuits are sequentially selected under the control of a select signal generating circuit which generates select signals corresponding to the voltage boosting circuits by use of a row address strobe signal. According to the above-mentioned configuration, the number of the voltage boosting circuits is less than the number of banks in the memory device. Therefore, the area that the voltage boosting circuits or internal power supply voltage generating circuits occupy on a chip does not increase in proportion to the increase in the number of banks.

Abstract: An integrated circuit memory device includes a memory cell block including a memory cell array which has a plurality of odd and even numbered subword lines extending therethrough. A first decoder is disposed at a top side of the memory cell block, which receives a first row address and generate a plurality of first control signals in response thereto. A second decoder is disposed at a bottom side of the memory cell block, which receives the first row address and generate a plurality of second control signals in response thereto. A row decoder receives a second row address and generates a word line signal in response thereto.

Abstract: A semiconductor memory device with a cascaded burn-in test capability for a plurality of memory cell blocks. A delayed feedback signal is communicated between memory cell block selection circuits to create the cascade burn-in.

Abstract: A semiconductor memory device includes a sub-wordline and a bit line connected to a memory cell, a sub-wordline driver for signaling the sub-wordline, and a main word decoder and a sub-word decoder, for selecting the sub-wordline driver in response to an external input address signal, wherein the wordline driver includes an NMOS transistor switch connected between a main wordline which is an output of the main word decoder and the sub-wordline, and wherein the logic "high" voltage level of a first control signal which controls the switch is lower than that of a signal output to the sub-wordline. The semiconductor memory device having the sub-wordline driver allows the internal power supply voltage to be used as the power supply voltage of the main word decoder. Accordingly, the reliability of a gate oxide film of a transistor constituting the main word decoder is improved, which lengthens the life of the semiconductor memory device.

Abstract: A burn-in stress control circuit for an integrated memory device, such as DRAM, includes a first logic gate for receiving a burn-in enable signal and outputting an inverted burn-in enable signal, a resistor having a first terminal connected to the input terminal of the first logic gate, a first capacitor connected between the second terminal of the resistor and ground. A first transistor having a control terminal connected to the second terminal of the resistor and a first main terminal connected to a source voltage, is activated only when the burn-in enable signal is a high logic signal, thereby outputting the source voltage to a second main terminal of the first transistor. A second transistor having a control terminal connected to an output terminal of the first logic gate, a first main terminal connected to ground and a second main terminal connected to the second main terminal of the first transistor, is activated only when the burn-in enable signal is a low logic signal.

Abstract: An integrated circuit memory device includes a memory cell array including a plurality of odd and even numbered subword lines extending therethrough. A predecoder receives a row address and generates a plurality of predecoding signals in response thereto, and a row decoder receives the row address and generates a word line signal in response thereto. A first driver block includes a first plurality of word line drive circuits adjacent the memory cell array wherein each of the word line drive circuits of the first plurality is connected to a respective odd numbered subword line of the memory cell array. A first plurality of subword line drive circuits drive the respective odd numbered subword lines responsive to odd numbered predecoding signals and the word line signal.

Abstract: A pulse generating circuit for use in a semiconductor memory device is triggered by a transition of an input logic signal, to provide an output pulse having a predetermined pulse width or period. Feedback from the output pulse is used to isolate the input signal once the output pulse has begun, so as to prevent premature truncation of the output pulse if the input signal changes state during the output pulse period. This pulse generator is particularly advantageous in high-speed semiconductor memory integrated circuits where the input pulse may be relatively brief.

Abstract: A circuit which controls a self-refresh period of a semiconductor memory device includes a pulse generating circuit which outputs a periodic pulse train in response to an external control signal, a frequency-dividing circuit which outputs a plurality of pulse trains having different respective periods by frequency-dividing the pulse train, at least one temperature detector which detects an ambient temperature of the memory device and outputs a temperature detection signal when the ambient temperature exceeds a predetermined threshold level, at least one voltage detecting circuit which detects a power supply voltage applied to the memory device and outputs a voltage detection signal when the power supply voltage reaches a predetermined level, a combination pulse train generating circuit which outputs a plurality of combination pulse trains by variously combining the plurality of pulse trains output by the frequency-dividing circuit, and a pulse selecting circuit which outputs a self-refresh master clock by sel