Abstract: Disclosed is a burn-in test circuit and method of a semiconductor memory device which is capable of applying a stress voltage simultaneously to a plurality of word lines and which is operative when the device is in either a wafer or package state. The disclosed burn-in test circuit and method includes the capability of fusably disabling burn-in test operations in the memory device once the burn-in test is completed. The burn-in test circuit includes a burn-in enable signal generator for receiving a predetermined timing of external signals by which the burn-in test is selected, and for generating a burn-in enable signal in response. A row address decoder, responsive to the burn-in enable signal, places the word lines of the device in a high-impedance state so that a word line stress input unit can simultaneously apply a stress voltage to the word lines to perform the burn-in test. Upon completion of the burn-in test, the burn-in enable signal generator fusably disables the burn-in enable signal.