Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

Abstract: A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

Abstract: A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.

Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

Abstract: Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.

Abstract: Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.

Abstract: An electrostatic discharge semiconductor device can include a first conductivity type substrate that includes inner first conductivity type wells therein and a plurality of gate electrodes that are on an active region of the substrate. A second conductivity type well can be located in the substrate beneath the plurality of gate electrodes including at least one slit therein providing electrical contact between the inner first conductivity type wells and a first conductivity type outer well outside the active region.

Abstract: In a method of detecting metal line failures for a full-chip, a first net-list is converted to a second net-list. The first net-list includes first information related to elements and metal lines, and the second net-list includes second information susceptible to direct current analysis. Current densities of the metal lines are calculated by performing the direct current analysis on the second net-list. Defective metal lines among the metal lines are detected based on the current densities of the metal lines.

Abstract: A method of detecting a degradation of a semiconductor device including calculating a first number of first traps accumulated in a gate insulation layer of the semiconductor device over an operation time of the semiconductor device; calculating the second number of second traps accumulated at an interface between the gate insulation layer and a substrate over the operation time; and calculating the degradation of the semiconductor device relative to the operation time using the first number of the first traps and the second number of the second traps.

Abstract: An electrostatic discharge semiconductor device can include a first conductivity type substrate that includes inner first conductivity type wells therein and a plurality of gate electrodes that are on an active region of the substrate. A second conductivity type well can be located in the substrate beneath the plurality of gate electrodes including at least one slit therein providing electrical contact between the inner first conductivity type wells and a first conductivity type outer well outside the active region.

Abstract: A modeling circuit includes a field-effect transistor, a first current source, a first bipolar transistor, a second current source and a second bipolar transistor. The first bipolar transistor and the second bipolar transistor are parasitic bipolar transistors that are arranged symmetrically to each other. Therefore, the modeling circuit can be used in simulating the field effect transistors reflecting electrostatic-discharge characteristic regardless of the polarity of a source and a drain.

Abstract: In a method of detecting metal line failures for a full-chip, a first net-list is converted to a second net-list. The first net-list includes first information related to elements and metal lines, and the second net-list includes second information susceptible to direct current analysis. Current densities of the metal lines are calculated by performing the direct current analysis on the second net-list. Defective metal lines among the metal lines are detected based on the current densities of the metal lines.

Abstract: A method of detecting a degradation of a semiconductor device including calculating a first number of first traps accumulated in a gate insulation layer of the semiconductor device over an operation time of the semiconductor device; calculating the second number of second traps accumulated at an interface between the gate insulation layer and a substrate over the operation time; and calculating the degradation of the semiconductor device relative to the operation time using the first number of the first traps and the second number of the second traps.

Abstract: A modeling circuit includes a field-effect transistor, a first current source, a first bipolar transistor, a second current source and a second bipolar transistor. The first bipolar transistor and the second bipolar transistor are parasitic bipolar transistors that are arranged symmetrically to each other. Therefore, the modeling circuit can be used in simulating the field effect transistors reflecting electrostatic-discharge characteristic regardless of the polarity of a source and a drain.

Abstract: A gate capacitance of a MOS transistor is determined by (a) measuring the gate capacitance and dissipation factor; (b) obtaining a channel resistance and a tunneling resistance; (c) setting an initial capacitance and an error dissipation factor; (d) calculating a direct dissipation factor using the channel resistance, the tunneling resistance, and the initial capacitance; (e) calculating a calculated dissipation factor using the error dissipation factor, the direct dissipation factor, and the measured dissipation factor; (f) calculating a calculated capacitance using the channel resistance, the tunneling resistance, the initial capacitance, the error dissipation factor, and the measured dissipation factor; and (g) detecting the initial capacitance as an accurate gate capacitance of the transistor if it is determined that the calculated capacitance is equal to the measured capacitance and the calculated dissipation factor is equal to the measured dissipation factor, and otherwise repeating steps (c) through (g

Abstract: An improved method for extrapolating worst-case Simulation Program with Integrated Circuit Emphasis (SPICE) model parameters for an integrated circuit including manufacturing semiconductor devices, measuring typical data and worst-case data with respect to various electrical characteristics of the manufactured devices, determining a set of typical SPICE model parameters using the typical data, and determining a set of worst-case SPICE model parameters using the typical data and the worst-case data. Determining the set of worst-case SPICE model parameters preferably includes extrapolating statistical model parameters using the typical data and the worst-case data and determining the set of worst-case SPICE model parameters using the statistical model parameters.

Abstract: A gate capacitance of a MOS transistor is determined by (a) measuring the gate capacitance and dissipation factor; (b) obtaining a channel resistance and a tunneling resistance; (c) setting an initial capacitance and an error dissipation factor; (d) calculating a direct dissipation factor using the channel resistance, the tunneling resistance, and the initial capacitance; (e) calculating a calculated dissipation factor using the error dissipation factor, the direct dissipation factor, and the measured dissipation factor; (f) calculating a calculated capacitance using the channel resistance, the tunneling resistance, the initial capacitance, the error dissipation factor, and the measured dissipation factor; and (g) detecting the initial capacitance as an accurate gate capacitance of the transistor if it is determined that the calculated capacitance is equal to the measured capacitance and the calculated dissipation factor is equal to the measured dissipation factor, and otherwise repeating steps (c) through (g