Abstract: A trusted processor saves and restores context and data stored at a frame buffer of a GPU concurrent with initialization of a CPU of the processing system. In response to detecting that the GPU is powering down, the trusted processor accesses the context of the GPU and data stored at a frame buffer of the GPU via a high-speed bus. The trusted processor stores the context and data at a system memory, which maintains the context and data while the GPU is powered down. In response to detecting that the GPU is powering up again, the trusted processor restores the context and data to the GPU, which can be performed concurrently with initialization of the CPU.

Abstract: Method and apparatus are provided wherein, in one example embodiment, a gaming machine includes a computing platform and a software program executing on the computing platform to provide a gaming experience to a user of the gaming machine, and there are provided one or more hardware or software components operative on the computing platform to detect faults occurring on the platform. At least one fault recovery software component is also operative on the gaming platform, and the fault recovery software component is adapted to operate in response to the detection of a fault.

Abstract: Example embodiments are directed to external control of peripheral devices through a communication proxy of an electronic wagering game machine in a wagering game network. In a particular embodiment, an electronic wagering game machine includes a central processing unit (CPU); at least one peripheral device in data communication with the CPU; and a data communication interface in data communication with the CPU to enable data communication with an external system via an external system interface, the data communication interface including a first communication mode to control data communication between the external system and the at least one peripheral device, the data communication interface including a second communication mode to enable a communication proxy that optionally relinquishes control of the data communication between the external system and the at least one peripheral device.

Abstract: Example embodiments are directed to external control of peripheral devices through a communication proxy of an electronic wagering game machine in a wagering game network. In a particular embodiment, an electronic wagering game machine includes a central processing unit (CPU); at least one peripheral device in data communication with the CPU; and a data communication interface in data communication with the CPU to enable data communication with an external system via an external system interface, the data communication interface including a first communication mode to control data communication between the external system and the at least one peripheral device, the data communication interface including a second communication mode to enable a communication proxy that optionally relinquishes control of the data communication between the external system and the at least one peripheral device.

Abstract: Method and apparatus are provided wherein, in one example embodiment, a gaming machine includes a computing platform and a software program executing on the computing platform to provide a gaming experience to a user of the gaming machine, and there are provided one or more hardware or software components operative on the computing platform to detect faults occurring on the platform. At least one fault recovery software component is also operative on the gaming platform, and the fault recovery software component is adapted to operate in response to the detection of a fault.

Abstract: An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

Abstract: Methods and apparatus for monitoring wagering game machines in a network are described herein. In one embodiment, a method for monitoring wagering game machines in a network includes receiving, in a wagering game machine, a wager associated with a wagering game. The method can also include receiving status information associated with a peripheral device or other component of the wagering game machine and transmitting diagnostic information indicating whether the peripheral device or other component needs service, wherein the diagnostic information is based at least in part on the status information.

Abstract: An image data processing system. According to the arrangement of the image sensor, two color dots having higher light intensity than the other two color dots in a white balance status are disposed on diagonal positions of the pixel group. The higher light intensity color such as green and white carry more luminance information than red and blue colors so that high intensity colors of green and white shall be arranged in diagonal line to improve the perceived luminance balance so that the distribution of green and white dots in an image sensor is more homogeneous and visual perception friendly than if green and white dots are arranged on vertical or horizontal lines. On the other hand, such diagonal arrangement of four primary colors image sensor is aligned with the four primary colors pixel pattern of RGBW display.

Abstract: The invention relates to a color matching method for transforming a color representation of a first set of color primaries with a plurality of first signals to a second set of color primaries with a plurality of second signals in a first domain. The color matching method of the invention is to consider the characteristics of human visual perception. Since human is more sensitive to the luminous intensity than chrominance, the color matching method of the invention is considered to match the luminous intensity. The color matching method of the invention can minimize the intensity difference by utilizing the optimality of resource distribution. An additional step of smoothing the intensity difference among color primaries at the level of color primaries is appended. It enhances the visual quality especially for the images with a gradual change in numerous levels of color. Besides, when the color is outside the gamut, we keep the information of luminance by adding extra white.

Abstract: The invention relates to a display and an image data processing system. According to the arrangement of the display, two color dots having lower light intensity than the other two color dots in a white balance status are disposed on diagonal positions of the pixel group. Therefore, the display of the invention can improve the color balance in the pixel group to avoid visible dark vertical line. The image data processing system of the invention utilizes the weighted dot rendering device for pre-compressing data. We can expect that the video compressed data size or the video transmission speed is reduced accordingly to a ratio of ? (¼ in the case of RGBW of 2×2 matrix arrangement because white (W) can be regenerated from the corresponding R, G, B), thus storage memory and transmission bandwidth can be reduced considerably without degrading the visual perception of the video quality on the proprietary VP display.

Abstract: The invention relates to a display and a weighted dot rendering method. The display comprises a plurality of pixel groups, each pixel group comprising a plurality of dots arranged in a predetermined identical matrix form, each pixel group having at least one first color dot, at least one second color dot and at least one third color dot, the pixel groups arranged in a matrix manner so as to form the display, wherein each color dot has a plurality of sides adjacent to the other dots with different color, and each color dot represents a luminance and a chrominance of a corresponding full color pixel data by grouping with neighboring dots to form a plurality of overlapping full color dynamics pixel groups.

Abstract: An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

Abstract: A multiplexor having a single event upset (SEU) hardened data keeper circuit is disclosed. The multiplexor includes a precharge transistor, an isolation transistor, an invertor, and an SEU immune storage cell. Both the gate of the precharge transistor and the gate of the isolation transistor are connected to a clock signal. The SEU immune storage cell has a first access node and a second access node. The first access node is complementary to the second access node. The first access node is connected to the precharge transistor and the second access node is connected to the isolation transistor. The invertor is coupled between the precharge transistor and the isolation transistor.

Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The first and second sets of isolation transistors are coupled to the first and second set of cross-coupled transistors, respectively, such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.