Abstract: A method is provided for initializing an electronic circuit in dependence on an externally applied voltage. The electronic circuit contains a first input circuit and further circuit elements. In a first step, a first enable signal for the operation of the input circuit and a further enable signal for the operation of the further circuit elements are deactivated if the voltage falls below a first threshold. In a second step, the first enable signal for the operation of an input circuit is activated and the further enable signal for the operation of the further circuit elements is deactivated if the voltage exceeds the first threshold. This is followed by the reception, with the first input circuit, of a chip select signal for the activation of the electronic circuit and of a code word at a terminal for the command bus. The activation of the further enable signal for the operation of the further circuit elements takes place if the received chip select signal and the received code word have predetermined values.

Abstract: A method is provided for initializing an electronic circuit in dependence on an externally applied voltage. The electronic circuit contains a first input circuit and further circuit elements. In a first step, a first enable signal for the operation of the input circuit and a further enable signal for the operation of the further circuit elements are deactivated if the voltage falls below a first threshold. In a second step, the first enable signal for the operation of an input circuit is activated and the further enable signal for the operation of the further circuit elements is deactivated if the voltage exceeds the first threshold. This is followed by the reception, with the first input circuit, of a chip select signal for the activation of the electronic circuit and of a code word at a terminal for the command bus. The activation of the further enable signal for the operation of the further circuit elements takes place if the received chip select signal and the received code word have predetermined values.

Abstract: A charge pump arrangement and methods for operating a charge pump arrangement are disclosed. According to various embodiments, a charge pump arrangement may include: a charge pump circuit configured to convert an input voltage into an output voltage based on a pump clock signal; a feedback path configured to provide a feedback signal representing the output voltage of the charge pump circuit; and a control circuit configured to receive a clock signal and to control the output voltage of the charge pump circuit by controlling the pump clock signal based on the feedback signal and the clock signal.

Abstract: A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The method includes determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; performing, by the control circuit, a predetermined action if the control circuit determination is positive; and storing, in a memory, the determined cell current at predetermined times, and to store the determined cell current change rate.

Abstract: A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines.

Abstract: A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.

Abstract: A charge pump arrangement and methods for operating a charge pump arrangement are disclosed. According to various embodiments, a charge pump arrangement may include: a charge pump circuit configured to convert an input voltage into an output voltage based on a pump clock signal; a feedback path configured to provide a feedback signal representing the output voltage of the charge pump circuit; and a control circuit configured to receive a clock signal and to control the output voltage of the charge pump circuit by controlling the pump clock signal based on the feedback signal and the clock signal.

Abstract: According to one embodiment, a circuit is described including a circuit component configured to switch from a first state into a second state including a node whose potential changes by a predetermined voltage when the circuit component switches from the first state into the second state, a line coupled with the node wherein the switching of the circuit component from the first state into the second state draws or injects a predetermined charge from or into the line, a capacitor coupled to the line and a compensation circuit configured to generate a predetermined multiple of the predetermined voltage and to compensate the charge drawn from or injected into the line by driving the capacitor with the multiple of the predetermined voltage.

Abstract: A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.

Abstract: A circuit having a memory element coupled between and having a full voltage between two supply rails; and a detection unit coupled to the memory element and configured to maintain a substantially constant biasing of the memory element while simultaneously detecting current flow through the memory element.

Abstract: A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage.

Abstract: A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

Abstract: A current mode converter includes a converter stage comprising a first switch, a second switch, an inductor, and a capacitor, and a digital-to-analog converter configured to convert a digital target current signal to an analog current signal. The current mode converter further includes a slope compensation circuit coupled to the digital-to-analog converter and is configured to convert the analog target current signal to a slope compensated analog target signal. A comparator is coupled to the converter stage and the slope compensation stage and is configured to generate and output a signal when a value of an actual analog signal is equal to a value of the slope compensated analog target signal.

Abstract: A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

Abstract: According to one embodiment, a circuit is described including a circuit component configured to switch from a first state into a second state including a node whose potential changes by a predetermined voltage when the circuit component switches from the first state into the second state, a line coupled with the node wherein the switching of the circuit component from the first state into the second state draws or injects a predetermined charge from or into the line, a capacitor coupled to the line and a compensation circuit configured to generate a predetermined multiple of the predetermined voltage and to compensate the charge drawn from or injected into the line by driving the capacitor with the multiple of the predetermined voltage.

Abstract: A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage.

Abstract: A current mode converter includes a converter stage comprising a first switch, a second switch, an inductor, and a capacitor, and a digital-to-analog converter configured to convert a digital target current signal to an analog current signal. The current mode converter further includes a slope compensation circuit coupled to the digital-to-analog converter and is configured to convert the analog target current signal to a slope compensated analog target signal. A comparator is coupled to the converter stage and the slope compensation stage and is configured to generate and output a signal when a value of an actual analog signal is equal to a value of the slope compensated analog target signal.

Abstract: A transmission gate includes first and second transmission path terminals, a series connection of first and second field effect transistors (FETs), and a control circuit. The channels of the first and second FETs are coupled in series between the first transmission path terminal and the second transmission path terminal, such that a channel contact of the first FET is coupled to the second transmission path terminal and a channel contact of the second FET is coupled to the first transmission path terminal.

Abstract: A transmission gate includes first and second transmission path terminals, a series connection of first and second field effect transistors (FETs), and a control circuit. The channels of the first and second FETs are coupled in series between the first transmission path terminal and the second transmission path terminal, such that a channel contact of the first FET is coupled to the second transmission path terminal and a channel contact of the second FET is coupled to the first transmission path terminal.

Abstract: A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.