Patents by Inventor Giacomo GABRIELLI

Giacomo GABRIELLI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250036485
    Abstract: Provided is a data stream processor comprising: a configurable compute unit comprising plural processing units each configured to receive at least one portion of input data and process the at least one portion of a repetitive arithmetical/logical operation on the data; an input memory unit in electronic communication with the configurable compute unit and configured to supply at least one portion of the input data to at least one of the plural processing units in the configurable compute unit; and at least one accumulator unit in electronic communication with the configurable compute unit and configured to receive at least two portions of processed data from the configurable compute unit and to output accumulated data; wherein each of the plural processing units is further configured to forward its processed data to a next processing unit and/or to an accumulator unit.
    Type: Application
    Filed: July 24, 2024
    Publication date: January 30, 2025
    Applicant: Arm Limited
    Inventors: Balaji Venu, Metin Gokhan Ünal, Giacomo Gabrielli, Damian Piotr Modrzyk, Dino Santoro
  • Publication number: 20250036632
    Abstract: Provided is a data stream processor comprising a streamed data transceiver interface, a structure of processing units configurable to transform data received from a data source over the streamed data transceiver interface according to a specified output requirement, and a configuration unit operable in electronic communication with a data consumer to receive an output requirement and to configure the operation and linkage of a processing unit in the structure of processing units to transform input data to output data according to the specified output requirement; wherein the structure of processing units is further operable to provide the output data for output over the streamed data transceiver interface.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 30, 2025
    Applicant: Arm Limited
    Inventors: Damian Piotr MODRZYK, Metin Gokhan ÜNAL, Giacomo GABRIELLI, Balaji VENU
  • Publication number: 20250037227
    Abstract: Provided is a graphics processing unit comprising a texture unit, an execution unit, and a machine-learning neural network engine, all configured in a pipeline in electronic communication with an integrated cache memory; and a visual data processing engine comprising a configurable stencil processor integrated into the pipeline, in electronic communication with the integrated cache memory, and configured to execute repetitive image-to-image processing instructions on visual data fetched from the integrated cache memory; wherein a graphics processing unit scheduler is configured to provide a job control function for the visual data processing engine; and wherein the visual data processing engine is configured responsively to the graphics processing unit scheduler to operate in parallel with at least one of the texture unit, the execution unit, or the machine-learning neural network engine using a separate dataflow.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 30, 2025
    Applicant: Arm Limited
    Inventors: Damian Piotr Modrzyk, Metin Gokhan Ünal, Giacomo Gabrielli, Balaji Venu
  • Publication number: 20250028530
    Abstract: There is provided a processing apparatus comprising decoder circuitry. The decoder circuitry is configured to generate control signals in response to an instruction. The processing apparatus further comprises processing circuitry which comprising a plurality of processing lanes. The processing circuitry is configured, in response to the control signals, to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing for that processing lane is enabled. The processing apparatus further comprises control circuitry to monitor each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes and to modify the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane meeting one or more predetermined conditions.
    Type: Application
    Filed: October 18, 2022
    Publication date: January 23, 2025
    Applicant: Arm Limited
    Inventors: Mbou Eyole, Michael Alexander Kennedy, Giacomo Gabrielli
  • Patent number: 12182261
    Abstract: A data processing apparatus is provided which controls the use of data in respect of a further operation. The data processing apparatus identifies whether data is trusted or untrusted by identifying whether or not the data was determined by a speculatively executed resolve-pending operation. A permission control unit is also provided to control how the data can be used in respect of a further operation according to a security policy while the speculatively executed operation is still resolve-pending.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 31, 2024
    Assignee: Arm Limited
    Inventors: Alastair David Reid, Albin Pierrick Tonnerre, Frederic Claude Marie Piry, Peter Richard Greenhalgh, Ian Michael Caulfield, Timothy Hayes, Giacomo Gabrielli
  • Publication number: 20240370263
    Abstract: There is provided a data processing apparatus and a method of operating a data processing apparatus. The data processing apparatus comprises a plurality of processing elements connected via a network on a single chip arranged to form a triggered spatial architecture. Each processing element comprises front end circuitry configured to generate triggered instructions which are passed to decode circuitry to cause the processing element to perform processing operations. Some processing elements are configured to operate in a producing mode in which the processing element transmits the triggered instructions as consumer instructions to be executed by each of a set of processing elements when operating in a consuming mode. Some processing elements are configured to operate in the consuming mode in which the processing elements retrieve consumer instructions transmitted from a processing element operating in a producing mode, and pass the consumer instructions to the decode circuitry.
    Type: Application
    Filed: June 22, 2022
    Publication date: November 7, 2024
    Applicant: Arm Limited
    Inventors: Balaji Venu, Mbou Eyole, Giacomo Gabrielli
  • Patent number: 12131155
    Abstract: An apparatus and method are provided for speculatively vectorising program code. The apparatus includes processing circuitry for executing program code, the program code including an identified code region comprising at least a plurality of speculative vector memory access instructions. Execution of each speculative vector memory access instruction is employed to perform speculative vectorisation of a series of scalar memory access operations using a plurality of lanes of processing. Tracking storage is used to maintain, for each speculative vector memory access instruction, tracking information providing an indication of a memory address being accessed within each lane. Checking circuitry then references the tracking information during execution of the identified code region by the processing circuitry, in order to detect any inter lane memory hazard resulting from the execution of the plurality of speculative vector memory access instructions.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 29, 2024
    Assignees: Arm Limited, The Chancellor, Masters and Scholars of the University of Cambridge
    Inventors: Peng Sun, Timothy Martin Jones, Giacomo Gabrielli
  • Publication number: 20240296132
    Abstract: There is provided a data processing apparatus and method. The data processing apparatus comprises a plurality of processing elements connected via a network arranged on a single chip to form a spatial architecture. Each processing element comprising processing circuitry to perform processing operations and memory control circuitry to perform data transfer operations and to issue data transfer requests for requested data to the network. The memory control circuitry is configured to monitor the network to retrieve the requested data from the network. Each processing element is further provided with local storage circuitry comprising a plurality of local storage sectors to store data associated with the processing operations, and auxiliary memory control circuitry to monitor the network to detect stalled data (S60).
    Type: Application
    Filed: June 21, 2022
    Publication date: September 5, 2024
    Applicant: Arm Limited
    Inventors: Mbou Eyole, Giacomo Gabrielli, Balaji Venu
  • Patent number: 12045622
    Abstract: One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: July 23, 2024
    Assignee: Arm Limited
    Inventors: Matthew James Walker, Mbou Eyole, Giacomo Gabrielli, Balaji Venu
  • Publication number: 20240220269
    Abstract: Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 4, 2024
    Applicant: Arm Limited
    Inventors: Mbou Eyole, Giacomo Gabrielli, Balaji Venu
  • Patent number: 11977896
    Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: May 7, 2024
    Assignee: Arm Limited
    Inventors: Matthew James Walker, Mbou Eyole, Giacomo Gabrielli, Balaji Venu, Wei Wang
  • Patent number: 11966739
    Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: April 23, 2024
    Assignee: Arm Limited
    Inventors: Matthew James Walker, Mbou Eyole, Giacomo Gabrielli, Balaji Venu
  • Publication number: 20240086201
    Abstract: One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Matthew James WALKER, Mbou EYOLE, Giacomo GABRIELLI, Balaji VENU
  • Publication number: 20240086196
    Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Matthew James WALKER, Mbou EYOLE, Giacomo GABRIELLI, Balaji VENU
  • Publication number: 20240086202
    Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Inventors: Matthew James WALKER, Mbou EYOLE, Giacomo GABRIELLI, Balaji VENU, Wei WANG
  • Patent number: 11797415
    Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 24, 2023
    Assignee: Arm Limited
    Inventors: Timothy Hayes, Giacomo Gabrielli, Matthew James Horsnell
  • Publication number: 20230325194
    Abstract: A data processing apparatus and a method for processing data are disclosed. The data processing apparatus comprises: multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Thread control circuitry collects runtime data indicative of a performance metric relating to the processing operations. Decoder circuitry is responsive to a detach instruction in a first micro-thread of instructions executed in a first execution context defining a first architectural state, the detach instruction specifying an address, to provide detach control signals to the thread control circuitry.
    Type: Application
    Filed: August 26, 2021
    Publication date: October 12, 2023
    Inventors: Syed Ali Mustafa ZAIDI, Giacomo GABRIELLI
  • Publication number: 20220236990
    Abstract: An apparatus and method are provided for speculatively vectorising program code. The apparatus includes processing circuitry for executing program code, the program code including an identified code region comprising at least a plurality of speculative vector memory access instructions. Execution of each speculative vector memory access instruction is employed to perform speculative vectorisation of a series of scalar memory access operations using a plurality of lanes of processing. Tracking storage is used to maintain, for each speculative vector memory access instruction, tracking information providing an indication of a memory address being accessed within each lane. Checking circuitry then references the tracking information during execution of the identified code region by the processing circuitry, in order to detect any inter lane memory hazard resulting from the execution of the plurality of speculative vector memory access instructions.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 28, 2022
    Inventors: Peng SUN, Timothy Martin JONES, Giacomo GABRIELLI
  • Publication number: 20220050909
    Abstract: A data processing apparatus is provided which controls the use of data in respect of a further operation. The data processing apparatus identifies whether data is trusted or untrusted by identifying whether or not the data was determined by a speculatively executed resolve-pending operation. A permission control unit is also provided to control how the data can be used in respect of a further operation according to a security policy while the speculatively executed operation is still resolve-pending.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 17, 2022
    Inventors: Alastair David REID, Albin Pierrick TONNERRE, Frederic Claude Marie PIRY, Peter Richard GREENHALGH, Ian Michael CAULFIELD, Timothy HAYES, Giacomo GABRIELLI
  • Publication number: 20210342248
    Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals.
    Type: Application
    Filed: August 30, 2019
    Publication date: November 4, 2021
    Inventors: Timothy HAYES, Giacomo GABRIELLI, Matthew James HORSNELL