Abstract: The present disclosure relates to a neural network comprising a first synapse circuit (106) configured to apply a first time delay to a first input signal (READ1) using a first resistive memory element (108) and to generate a first output signal at an output of the first synapse circuit by applying a first weight to the delayed first input signal; and a second synapse circuit (106) configured to apply a second time delay, different to the first time delay, to the first input signal, or to a second input signal (READN), using a second resistive memory element (108) and to generate a second output signal at an output of the second synapse circuit by applying a second weight to the delayed second input signal.

Abstract: The present disclosure relates to a synapse circuit of a spiking neural network comprising: at least one resistive switching memory device having a conductance that decays over time; and at least one programming circuit configured to store an eligibility trace by programming a resistive state of the at least one resistive memory device.

Abstract: The present disclosure relates to a neuron circuit of a spiking neural network comprising: a first resistive switching memory device having a conductance that decays over time; and a programming circuit configured to reset the resistive state of the first resistive switching element in response to a spike in an output voltage of the neuron circuit.

Abstract: Circuits for generating random weights, such as for neuromorphic processors, include a first voltage node (VDD) for providing a supply voltage for the circuit and a second voltage node (VG) at a given electric potential. A first circuit element (Ma1) has a first electric current carrier concentration for outputting a first circuit element output signal. A second circuit element (Mb1) has a second electric current carrier concentration for outputting a second circuit element output signal. The first and second circuit elements are located between the first and second voltage nodes, which have a given voltage difference therebetween. The first and second circuit element output signals are different due to the first and second electric carrier concentrations being mismatched. The circuit further includes a subtraction unit configured to generate a respective random weight, which is represented by a difference between the first and second circuit element output signals.

Abstract: Among other aspects, the present invention relates to a network comprising a plurality of interconnected core circuits (10) particularly arranged on several units (6), wherein each core circuit (10) comprises: an electronic array (8, 9) comprising a plurality of computing nodes (90) and a plurality of memory circuits (80) which is configured to receive incoming events, wherein each computing node (90) is configured to generate an event comprising a data packet when incoming events received by the respective computing node (90) satisfy a pre-defined criterion, and a circuit which is configured to append destination address and additional source information, particularly source core ID, to the respective data packet, and a local first router (R1) for providing intra-core connectivity and/or delivering events to intermediate level second router (R2) for inter-core connectivity and to higher level third router (R3) for inter-unit connectivity, and a broadcast driver (7) for broadcasting incoming events to all the

Abstract: The present disclosure relates to a routing circuit for routing signals between neuron circuits of an artificial neural network, the routing circuit comprising: a first memory cell (302) having an input coupled to a first input line (304) of the routing circuit and an output coupled to a first column line (308); a second memory cell (302) having an input coupled to a second input line (304) of the routing circuit and an output coupled to the first column line (308); and a first comparator circuit (310) configured to compare a signal (IREAD1) on the first column line (308) with a reference level, and to selectively assert a signal (VOUT1) on a first output line (312) of the routing circuit based on the comparison.

Abstract: A differential memristive circuit includes a normaliser; a first memristor connected between first top and bottom nodes, the first memristive element having a first adjustable resistance value; a first switch connected between the first bottom node and the normaliser; a second memristor connected between a second top node and a second bottom node the second memristor having a second adjustable resistance value; a second switch connected between the second bottom node and the normaliser; and a set of voltage sources that generate voltages greater than 0V. The set of voltage sources generate a first voltage value across the first memristor and a second voltage value across the second memristor. A first output signal depends on the first adjustable resistance value, while a second output signal depends on the second adjustable resistance value. A memristive circuit net output signal is obtained as the difference between the first and second output signals.

Abstract: A differential memristive circuit includes a normaliser; a first memristor connected between first top and bottom nodes, the first memristive element having a first adjustable resistance value; a first switch connected between the first bottom node and the normaliser; a second memristor connected between a second top node and a second bottom node the second memristor having a second adjustable resistance value; a second switch connected between the second bottom node and the normaliser; and a set of voltage sources that generate voltages greater than 0V. The set of voltage sources generate a first voltage value across the first memristor and a second voltage value across the second memristor. A first output signal depends on the first adjustable resistance value, while a second output signal depends on the second adjustable resistance value. A memristive circuit net output signal is obtained as the difference between the first and second output signals.

Abstract: Among other aspects, the present invention relates to a network comprising a plurality of interconnected core circuits (10) particularly arranged on several units (6), wherein each core circuit (10) comprises: an electronic array (8, 9) comprising a plurality of computing nodes (90) and a plurality of memory circuits (80) which is configured to receive incoming events, wherein each computing node (90) is configured to generate an event comprising a data packet when incoming events received by the respective computing node (90) satisfy a pre-defined criterion, and a circuit which is configured to append destination address and additional source information, particularly source core ID, to the respective data packet, and a local first router (R1) for providing intra-core connectivity and/or delivering events to intermediate level second router (R2) for inter-core connectivity and to higher level third router (R3) for inter-unit connectivity, and a broadcast driver (7) for broadcasting incoming events to all the