Patents by Inventor Giai Trinh

Giai Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7663401
    Abstract: A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: February 16, 2010
    Assignee: Lattice Semiconductor Corporation
    Inventors: Chi Minh Nguyen, Chan-Chi Jason Cheng, Timothy S. Swensen, Giai Trinh, Yi Chiang
  • Patent number: 5841165
    Abstract: A P-channel single-poly EPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel and, in some embodiments, over significant portions of P+ source and P+ drain regions. A poly-silicon floating gate overlies the tunnel oxide. A P diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. In this manner, the P diffusion region serves as a control gate for the memory cell. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions to cause the hot injection of electrons from the N-well/drain junction to the floating gate, while erasing is realized by biasing the floating gate, N-well, source and drain regions appropriately so as cause the tunneling of electrons from the floating gate to the N-well, the source, and the drain.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: November 24, 1998
    Assignee: Programmable Microelectronics Corporation
    Inventors: Shang-De Ted Chang, Jayson Giai Trinh
  • Patent number: 5796656
    Abstract: A row decoder circuit selectively provides suitable programming, reading, and erasing voltages to an associated memory array employing PMOS floating gate transistors as memory cells. In some embodiments, during programming, the row decoder circuit pulls a selected word line of the associated memory array high to a programming voltage on a first voltage line and maintains an un-selected word line at a predetermined potential. During reading, the row decoder circuit discharges the word line, if selected, to ground potential, and maintains the word line, if un-selected, at a predetermined potential. During erasing, the row decoder circuit charges the word line to a high negative voltage. The row decoder circuit includes isolation means to electrically isolate the word line of the associated memory array from undesirable potentials during programming, reading, and erasing operations.
    Type: Grant
    Filed: February 22, 1997
    Date of Patent: August 18, 1998
    Assignee: Programmable Microelectronics Corporation
    Inventors: Vikram Kowshik, Andy Teng-Feng Yu, Jayson Giai Trinh
  • Patent number: 5777926
    Abstract: A row decoder circuit selectively provides suitable programming, reading, and erasing voltages to an associated memory array employing PMOS floating gate transistors as memory cells. In some embodiments, during programming, the row decoder circuit pulls a selected word line of the associated memory array high to a programming voltage on a first voltage line and maintains an un-selected word line at a predetermined potential. During reading, the row decoder circuit discharges the word line, if selected, to ground potential, and maintains the word line, if un-selected, at a predetermined potential. During erasing, the row decoder circuit charges the word line to a high negative voltage. The row decoder circuit includes isolation means to electrically isolate the word line of the associated memory array from undesirable potentials during programming, reading, and erasing operations.
    Type: Grant
    Filed: October 24, 1996
    Date of Patent: July 7, 1998
    Assignee: Programmable Microelectronics Corporation
    Inventors: Jayson Giai Trinh, Vikram Kowshik, Andy Teng-Feng Yu