Abstract: A hardware network accelerator comprises a plurality of Ethernet communication interfaces, a plurality of memories, and a further memory. Each memory stores records comprising destination IP data identifying a destination IP address range. The further memory stores further records, wherein each record comprises next-hop data indicating a next-hop IP address, next-hop enable data, and network port data indicating an Ethernet communication interface. Each Ethernet communication interface is configured to obtain an IP packet, access in parallel the memories in order to read the records, select a record having a destination IP address range containing the destination IP address of the IP packet, read the further record associated with the selected record from the further memory, and select the indicated Ethernet communication interface. The selected Ethernet communication interface is configured to transmit an Ethernet frame comprising the IP packet based on the next-hop enable data and next-hop data.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: Test stimulus signals applied to at least one circuit under test are produced in a set of test stimulus generators as a function of test stimulus information loaded in test stimulus registers. Loading of the test stimulus information in the test stimulus registers is controlled as a function of test programming information loaded via a programming interface in a respective control register in a set of control registers. The test stimulus generators are activated as a function of the test programming information loaded in said control registers. Test outcome signals received from the at least one circuit under test are used to produce signature comparison signals, which are compared with respective programmable signature reference signals stored in a set of input signature registers, are produced in response to the signature comparison signals produced from the test outcome signals failing to match with the respective reference signals.

Abstract: A system, for use in providing media access control (MAC)/router/switch/gateway features in an on-board communication network in a vehicle, includes MAC controllers configured to provide a MAC port layer controlling exchange of information over a data link, virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs, a software (SW) Ethernet port configured to receive from a host programming/configuration information for the system, a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (LMEM), and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation with the LMEM via the local memory controller.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Abstract: An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Abstract: Test stimulus signals applied to at least one circuit under test are produced in a set of test stimulus generators as a function of test stimulus information loaded in test stimulus registers. Loading of the test stimulus information in the test stimulus registers is controlled as a function of test programming information loaded via a programming interface in a respective control register in a set of control registers. The test stimulus generators are activated as a function of the test programming information loaded in said control registers. Test outcome signals received from the at least one circuit under test are used to produce signature comparison signals, which are compared with respective programmable signature reference signals stored in a set of input signature registers, are produced in response to the signature comparison signals produced from the test outcome signals failing to match with the respective reference signals.

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: An embodiment circuit comprises a set of input terminals configured to receive input digital signals which carry input data, a set of output terminals configured to provide output digital signals which carry output data, and computing circuitry configured to produce the output data as a function of the input data. The computing circuitry comprises a set of multiplier circuits, a set of adder-subtractor circuits, a set of accumulator circuits, and a configurable interconnect network. The configurable interconnect network is configured to selectively couple the multiplier circuits, the adder-subtractor circuits, the accumulator circuits, the input terminals and the output terminals in at least two processing configurations. In a first configuration, the computing circuitry is configured to compute the output data according to a first set of functions, and, in a second configuration, the computing circuitry is configured to compute the output data according to a different set of functions.

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Abstract: An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.

Abstract: An embodiment circuit comprises a set of input terminals configured to receive input digital signals which carry input data, a set of output terminals configured to provide output digital signals which carry output data, and computing circuitry configured to produce the output data as a function of the input data. The computing circuitry comprises a set of multiplier circuits, a set of adder-subtractor circuits, a set of accumulator circuits, and a configurable interconnect network. The configurable interconnect network is configured to selectively couple the multiplier circuits, the adder-subtractor circuits, the accumulator circuits, the input terminals and the output terminals in at least two processing configurations. In a first configuration, the computing circuitry is configured to compute the output data according to a first set of functions, and, in a second configuration, the computing circuitry is configured to compute the output data according to a different set of functions.

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition.