Abstract: In a Schottky field effect MESFET transistor including a semiconductor substrate and source, gate and drain electrodes, the electrical resistance of the gate is reduced to substantially zero by implementing the gate electrode as a sheet of metallization which bypasses a portion of the source electrode and which is spaced from the source electrode by a layer of air or the like. The MESFET transistor may be fabricated by providing drain and source electrodes on a semiconductor substrate with the electrodes situated side-by-side. Photoresist is applied over at least the source electrode while leaving exposed (a) a first portion of the substrate surface between the source and drain electrodes and (b) a second portion of the substrate surface situated on an opposite side of the source electrode and which is used as a bonding pad location. Gate metallization is then formed over the photoresist and in contact with the first and second areas of the substrate surface.

Abstract: In a Schottky field effect MESFET transistor including a semiconductor substrate and source, gate and drain electrodes, the electrical resistance of the gate is reduced to substantially zero by implementing the gate electrode a sheet of metallization which bypasses a portion of the source electrode and which is spaced from the source electrode by a layer of air or the like. The MESFET transistor may be fabricated by providing drain and source electrodes as on a semiconductor substrate with the electrodes situated side-by-side. Photoresist is applied over at least the source electrode while leaving exposed (a) a first portion of the substrate surface between the source and drain electrodes and (b) a second portion of the substrate surface situated on an opposite side of the source electrode and which is used as a bonding pad location. Gate metallization is then formed over the photoresist and in contact with the first and second areas of the substrate surface.

Abstract: Grounding of source contacts (S) of flat devices and integrated circuits (of the FET type) is carried out according to the following process steps: a GaAs wafer is applied on a support and is covered on its free or rear face with photoresist; the latter is then etched along the border lines of the single FETs; the GaAs layer between contiguous FETs is removed also to make accessible the contacts S; a layer of noble metal is then deposited on the FET rear faces, so that it bridges the contacts S; the single metallized devices are disconnected from the initial support and finally are soldered to a package base.