Patents by Inventor Giampiero Sberno

Giampiero Sberno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7633805
    Abstract: A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 15, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Mario Micciche, Gianbattista Lo Giudice, Alberto Di Martino, Giampiero Sberno
  • Patent number: 7580289
    Abstract: A non-volatile memory device is proposed. The memory device includes a plurality of blocks of memory cells, each block having a common biasing node for all the memory cells of the block, biasing means for providing a biasing voltage, and selection means for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means and second switching means connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: August 25, 2009
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Antonino Conte, Giampiero Sberno, Mario Micciche', Enrico Castaldo
  • Publication number: 20080130361
    Abstract: A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
    Type: Application
    Filed: November 16, 2007
    Publication date: June 5, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Conte, Mario Micciche, Gianbattista Lo Giudice, Alberto Di Martino, Giampiero Sberno
  • Publication number: 20070007561
    Abstract: A non-volatile memory device is proposed. The memory device includes a plurality of blocks of memory cells, each block having a common biasing node for all the memory cells of the block, biasing means for providing a biasing voltage, and selection means for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means and second switching means connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.
    Type: Application
    Filed: May 25, 2006
    Publication date: January 11, 2007
    Inventors: Antonino Conte, Giampiero Sberno, Mario Micciche, Enrico Castaldo
  • Patent number: 6980458
    Abstract: A circuit for sensing a ferroelectric non-volatile information storage unit comprises a pre-charge circuit for applying a prescribed pre-charge voltage to a storage capacitor of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the storage capacitor, depending on an initial polarization state of the storage capacitor. A charge integration circuit integrates an electric charge proportional to the variation in polarization charge experienced by the storage capacitor. The charge integration circuit thus provides an output voltage depending on the polarization state of the storage capacitor.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: December 27, 2005
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Nicolas Demange, Salvatore Torrisi, Giampiero Sberno
  • Patent number: 6930907
    Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: August 16, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giampiero Sberno, Salvatore Torrisi, Nicolas Demange
  • Patent number: 6909626
    Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: June 21, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Torrisi, Giampiero Sberno, Nicolas Demange
  • Patent number: 6885574
    Abstract: A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: April 26, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Torrisi, Giampiero Sberno, Nicolas Demange
  • Patent number: 6795330
    Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: September 21, 2004
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Nicolas Demange, Salvatore Torrisi, Giampiero Sberno
  • Publication number: 20040015643
    Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.
    Type: Application
    Filed: March 28, 2003
    Publication date: January 22, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Torrisi, Giampiero Sberno, Nicolas Demange
  • Publication number: 20030234413
    Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.
    Type: Application
    Filed: April 14, 2003
    Publication date: December 25, 2003
    Applicant: STMicroelectronics S.r.I.
    Inventors: Giampiero Sberno, Salvatore Torrisi, Nicolas Demange
  • Publication number: 20030090925
    Abstract: A circuit for sensing a ferroelectric non-volatile information storage unit comprises a pre-charge circuit for applying a prescribed pre-charge voltage to a storage capacitor of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the storage capacitor, depending on an initial polarization state of the storage capacitor. A charge integration circuit integrates an electric charge proportional to the variation in polarization charge experienced by the storage capacitor. The charge integration circuit thus provides an output voltage depending on the polarization state of the storage capacitor.
    Type: Application
    Filed: October 18, 2002
    Publication date: May 15, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Nicolas Demange, Salvatore Torrisi, Giampiero Sberno
  • Publication number: 20030090926
    Abstract: A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 15, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Salvatore Torrisi, Giampiero Sberno, Nicolas Demange
  • Publication number: 20030058702
    Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state.
    Type: Application
    Filed: August 23, 2002
    Publication date: March 27, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Nicolas Demange, Salvatore Torrisi, Giampiero Sberno