Abstract: A protection circuit and method for protecting driven circuitry against voltage peaks in a radio frequency signal, “VRF”, past a predetermined voltage level “Vdetect”. The protection circuit includes an input for receiving the radio frequency signal. The protection circuit also includes at least one amplification stage coupled to the input. The amplification stage is operable to produce an amplified signal based on Vdetect?VRF. The protection circuit further includes a hold circuit operable to determine, from the amplified signal produced by the amplification stage, whether a peak voltage Vpeak of the radio frequency signal exceeds Vdetect. The hold circuit is operable to output a first detection value if Vpeak exceeds Vdetect. The hold circuit is operable to output a second detection value if Vpeak does not exceed Vdetect. The protection circuit also includes a latch circuit operable to latch the detection value outputted by the hold circuit.

Abstract: An attenuator arrangement comprising at least a first attenuation path configured to couple between a signal processing chain, SPC, and a measurement apparatus; said SPC comprising a first and second SPC terminal, said SPC configured to apply one or both of a gain and phase change on a signal passed between the SPC terminals; said measurement apparatus configured to measure one or both of the gain and the phase change applied by SPC by coupling to and receiving signals from said SPC terminals; wherein one of said first SPC terminal and said second SPC terminal is coupled to the measurement apparatus through said first attenuation path; and wherein the at least first attenuation path of the attenuator arrangement is configured to provide, selectively, for attenuation of the signal to the measurement apparatus to make the signal power of the signals from said SPC terminals more equal.

Abstract: An antenna switch circuit and an antenna circuit switching method. The circuit includes an antenna port, a termination port (e.g., for disposal of power reflected back from an antenna and received through the antenna port in a transmit mode), and a receive port (e.g., for receiving a signal from the antenna port via the antenna switch circuit in a receive mode). The circuit also includes a first switch coupled between the antenna port and the termination port. The circuit further includes a resonant inductance coupled between the receive port and the node located between the antenna port and the first switch. The circuit also includes a second switch coupled between a reference potential and a node located between the resonant inductance and the receive port.

Abstract: A circuit comprising: an input terminal; a first amplifier coupled to the input terminal of the circuit to receive an input signal; a first inductor having a first terminal coupled to the input terminal and a second terminal configured to be coupled to the ground terminal, wherein the first inductor is arranged with a second inductor and configured to magnetically couple therewith, wherein said second inductor is coupled to the first amplifier and is configured to sense a current through the amplifier.

Abstract: An antenna switch circuit and an antenna circuit switching method. The circuit includes an antenna port, a termination port (e.g., for disposal of power reflected back from an antenna and received through the antenna port in a transmit mode), and a receive port (e.g., for receiving a signal from the antenna port via the antenna switch circuit in a receive mode). The circuit also includes a first switch coupled between the antenna port and the termination port. The circuit further includes a resonant inductance coupled between the receive port and the node located between the antenna port and the first switch. The circuit also includes a second switch coupled between a reference potential and a node located between the resonant inductance and the receive port.

Abstract: A protection circuit and method for protecting driven circuitry against voltage peaks in a radio frequency signal, “VRF”, past a predetermined voltage level “Vdetect”. The protection circuit includes an input for receiving the radio frequency signal. The protection circuit also includes at least one amplification stage coupled to the input. The amplification stage is operable to produce an amplified signal based on Vdetect?VRF. The protection circuit further includes a hold circuit operable to determine, from the amplified signal produced by the amplification stage, whether a peak voltage Vpeak of the radio frequency signal exceeds Vdetect. The hold circuit is operable to output a first detection value if Vpeak exceeds Vdetect. The hold circuit is operable to output a second detection value if Vpeak does not exceed Vdetect. The protection circuit also includes a latch circuit operable to latch the detection value outputted by the hold circuit.

Abstract: An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.

Abstract: A RF switching arrangement (400) is described including a bias swap circuit (30). The bias swap circuit switches the bias voltage dependent on the state of the RF switch. This improves the performance of the RF switch without requiring charge pump circuitry.

Abstract: An attenuator arrangement comprising at least a first attenuation path configured to couple between a signal processing chain, SPC, and a measurement apparatus; said SPC comprising a first and second SPC terminal, said SPC configured to apply one or both of a gain and phase change on a signal passed between the SPC terminals; said measurement apparatus configured to measure one or both of the gain and the phase change applied by SPC by coupling to and receiving signals from said SPC terminals; wherein one of said first SPC terminal and said second SPC terminal is coupled to the measurement apparatus through said first attenuation path; and wherein the at least first attenuation path of the attenuator arrangement is configured to provide, selectively, for attenuation of the signal to the measurement apparatus to make the signal power of the signals from said SPC terminals more equal.

Abstract: An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.

Abstract: An RF switch for connecting an antenna to a transceiver is described. The RF switch includes a first switchable capacitor arranged between a first terminal and a common terminal and a second switchable capacitor arranged between a second terminal and the common terminal. Each of the first and second switchable capacitors are switchable between a pass state and a blocking state. The capacitance value in the pass state is higher than the capacitance value in the blocking state.

Abstract: A matching circuit comprising: an input-terminal configured to be connected to an active-circuit; an output-terminal configured to be connected to a downstream component; a current-source configured to provide a disabled-current; one or more diode-modules, each comprising a diode and a biasing-resistor in parallel with each other; and a reactive-matching-component that has a reactive impedance. The current source is configured to pass the disabled-current through the one or more diode-modules and the reactive-matching-component when the matching circuit is in a disabled-mode of operation such that they contribute to the impedance of the matching circuit between the input-terminal and the output-terminal.

Abstract: An RF switch for connecting an antenna to a transceiver is described. The RF switch includes a first switchable capacitor arranged between a first terminal and a common terminal and a second switchable capacitor arranged between a second terminal and the common terminal. Each of the first and second switchable capacitors are switchable between a pass state and a blocking state. The capacitance value in the pass state is higher than the capacitance value in the blocking state.

Abstract: A power supply ready indicator circuit is described. The power supply ready indicator circuit includes a first power-supply-ready-input interfacing with a first power supply rail; a second power-supply-ready-input interfacing with a second power supply rail; and a power ready indicator output. The power supply ready indicator circuit is configured to divide the voltage on the first power supply rail, and to compare the divided voltage with the second power supply rail voltage. The power supply ready indicator circuit generates a power ready signal on the power ready indicator output in response to the divided voltage value being greater than the second power supply rail voltage value. The final value of the first power supply rail voltage is greater than the final value of the second power supply rail voltage.

Abstract: A matching circuit comprising: an input-terminal configured to be connected to an active-circuit; an output-terminal configured to be connected to a downstream component; a current-source configured to provide a disabled-current; one or more diode-modules, each comprising a diode and a biasing-resistor in parallel with each other; and a reactive-matching-component that has a reactive impedance. The current source is configured to pass the disabled-current through the one or more diode-modules and the reactive-matching-component when the matching circuit is in a disabled-mode of operation such that they contribute to the impedance of the matching circuit between the input-terminal and the output-terminal.

Abstract: A power supply ready indicator circuit is described. The power supply ready indicator circuit includes a first power-supply-ready-input interfacing with a first power supply rail; a second power-supply-ready-input interfacing with a second power supply rail; and a power ready indicator output. The power supply ready indicator circuit is configured to divide the voltage on the first power supply rail, and to compare the divided voltage with the second power supply rail voltage. The power supply ready indicator circuit generates a power ready signal on the power ready indicator output in response to the divided voltage value being greater than the second power supply rail voltage value. The final value of the first power supply rail voltage is greater than the final value of the second power supply rail voltage.

Abstract: A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.

Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.

Abstract: An RF amplifier comprising an input-transistor having an input-transistor-base terminal, an input-transistor-collector terminal and an input-transistor-emitter terminal; a degeneration-component connected between the input-transistor-emitter terminal and a ground terminal; and a protection-transistor having a protection-transistor-base terminal, a protection-transistor-collector terminal and a protection-transistor-emitter terminal. The input-transistor-base terminal is connected to the protection-transistor-emitter terminal, and the protection-transistor-base terminal is connected to the input-transistor-emitter.