Abstract: A system and method for in-memory image processing. In some embodiments, a system includes a memory, a first neuron processing circuit, and a second neuron processing circuit. The first neuron processing circuit may be connected to a first plurality of bit lines of the memory, and the second neuron processing circuit may be connected to a second plurality of bit lines of the memory. The first neuron processing circuit may include a plurality of configurable processing circuits, each of the configurable processing circuits including: an artificial neuron for calculating the sign of a weighted sum of a plurality of single-bit digital input signals at respective inputs of the artificial neuron, and a plurality of multiplexers, each having an output connected to a respective input of the inputs of the artificial neuron.

Abstract: A quantized neural network circuit. The circuit may include a neuron processing element, the neuron processing element including a first neuron cluster and a second neuron cluster. The first neuron cluster may include: a first binary neuron, having a first input network with a first number of inputs; a second binary neuron, having a first input network with a second number of inputs, the second number being different from the first number; a plurality of multiplexers, each having an output connected to a respective input of the inputs of the first input network of the first binary neuron; and a plurality of flip-flops, each having an output connected to an input of a respective multiplexer of the plurality of multiplexers.

Abstract: A system and method for computing in memory with artificial neurons. According to an embodiment of the present disclosure, there is provided a system, including: a computer-readable memory; a neuron processing element communicatively connected to the computer-readable memory, the neuron processing element including: a plurality of configurable processing circuits each having a plurality of outputs and a plurality of inputs; and a network connecting one or more of the outputs of the configurable processing circuits to one or more of the inputs of the configurable processing circuits, each of the configurable processing circuits including: an artificial neuron having a plurality of inputs; and a register connected to the inputs of the artificial neuron.

Abstract: A quantized neural network circuit. The circuit may include a neuron processing element, the neuron processing element including a first neuron cluster and a second neuron cluster. The first neuron cluster may include: a first binary neuron, having a first input network with a first number of inputs; a second binary neuron, having a first input network with a second number of inputs, the second number being different from the first number; a plurality of multiplexers, each having an output connected to a respective input of the inputs of the first input network of the first binary neuron; and a plurality of flip-flops, each having an output connected to an input of a respective multiplexer of the plurality of multiplexers.

Abstract: A system and method for in-memory image processing. In some embodiments, a system includes a memory, a first neuron processing circuit, and a second neuron processing circuit. The first neuron processing circuit may be connected to a first plurality of bit lines of the memory, and the second neuron processing circuit may be connected to a second plurality of bit lines of the memory. The first neuron processing circuit may include a plurality of configurable processing circuits, each of the configurable processing circuits including: an artificial neuron for calculating the sign of a weighted sum of a plurality of single-bit digital input signals at respective inputs of the artificial neuron, and a plurality of multiplexers, each having an output connected to a respective input of the inputs of the artificial neuron.

Abstract: A system and method for computing in memory with artificial neurons. According to an embodiment of the present disclosure, there is provided a system, including: a computer-readable memory; a neuron processing element communicatively connected to the computer-readable memory, the neuron processing element including: a plurality of configurable processing circuits each having a plurality of outputs and a plurality of inputs; and a network connecting one or more of the outputs of the configurable processing circuits to one or more of the inputs of the configurable processing circuits, each of the configurable processing circuits including: an artificial neuron having a plurality of inputs; and a register connected to the inputs of the artificial neuron.