Patents by Inventor Gianbattista Lo Giudice

Gianbattista Lo Giudice has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10147490
    Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: December 4, 2018
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Francesca Grande, Francesco La Rosa, Gianbattista Lo Giudice, Giovanni Matranga
  • Publication number: 20180151231
    Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.
    Type: Application
    Filed: May 29, 2017
    Publication date: May 31, 2018
    Inventors: Francesca Grande, Francesco La Rosa, Gianbattista Lo Giudice, Giovanni Matranga
  • Patent number: 8619489
    Abstract: An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells for programming the selected memory cells; the first programming voltage requires a first transient period for reaching a first target value thereof. In the solution according to an embodiment of the present invention, the programming means includes means for maintaining the second programming voltage substantially equal to the first programming voltage during a second transient period being required by the second programming voltage to reach a second target value thereof.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: December 31, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Castaldo, Antonio Conte, Gianbattista Lo Giudice, Stefania Rinaldi
  • Patent number: 8437196
    Abstract: A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 7, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gianbattista Lo Giudice, Antonino Conte, Mario Micciche, Stefania Rinaldi
  • Patent number: 8406068
    Abstract: A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage is connected to an output branch and to a selection circuit, which receives a selection signal that controls switching of the latch stage. The latch stage is coupled to the supply line and to a reference potential line, which receives a reference voltage that can vary between a first reference value, when the supply voltage has the first operating value, and a second reference value, higher than the first reference value, when the supply voltage has the second operating value. An uncoupling stage is arranged between the latch stage and the selection circuit and uncouples them in the second operating condition, when the supply voltage and the reference voltage are at their second, high, value.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: March 26, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enrico Castaldo, Gianbattista Lo Giudice, Alfredo Signorello
  • Patent number: 8376237
    Abstract: Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 19, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gianbattista Lo Giudice, Enrico Castaldo, Antonino Conte
  • Publication number: 20110267891
    Abstract: An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells for programming the selected memory cells; the first programming voltage requires a first transient period for reaching a first target value thereof. In the solution according to an embodiment of the present invention, the programming means includes means for maintaining the second programming voltage substantially equal to the first programming voltage during a second transient period being required by the second programming voltage to reach a second target value thereof.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 3, 2011
    Applicant: STMicroelectronics S.r.I.
    Inventors: Enrico Castaldo, Antonio Conte, Gianbattista Lo Giudice, Stefania Rinaldi
  • Publication number: 20110069563
    Abstract: A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage is connected to an output branch and to a selection circuit, which receives a selection signal that controls switching of the latch stage. The latch stage is coupled to the supply line and to a reference potential line, which receives a reference voltage that can vary between a first reference value, when the supply voltage has the first operating value, and a second reference value, higher than the first reference value, when the supply voltage has the second operating value. An uncoupling stage is arranged between the latch stage and the selection circuit and uncouples them in the second operating condition, when the supply voltage and the reference voltage are at their second, high, value.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 24, 2011
    Applicant: STMicroelectronics S.r.l.
    Inventors: Enrico Castaldo, Gianbattista Lo Giudice, Alfredo Signorello
  • Publication number: 20110068179
    Abstract: Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 24, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Gianbattista Lo Giudice, Enrico Castaldo, Antonino Conte
  • Publication number: 20110069554
    Abstract: A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 24, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Gianbattista Lo Giudice, Antonino Conte, Mario Micciche, Stefania Rinaldi
  • Patent number: 7633805
    Abstract: A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 15, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Mario Micciche, Gianbattista Lo Giudice, Alberto Di Martino, Giampiero Sberno
  • Patent number: 7602230
    Abstract: An integrated control circuit for a charge pump includes a first device for regulating the output voltage of the charge pump and a second device for increasing the output voltage from the charge pump with a set ramp. The integrated circuit includes means for activating said first device and providing it with a first value of a supply signal in a first period of time and for activating the second device and providing it with a second value of the supply signal that is greater than the first value in a second period of time after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value to a second value that is greater than the first value, the second value being fixed by reactivation of the first device.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 13, 2009
    Assignee: STMicroelectronics S.R.L.
    Inventors: Enrico Castaldo, Antonino Conte, Gianbattista Lo Giudice
  • Publication number: 20080130361
    Abstract: A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
    Type: Application
    Filed: November 16, 2007
    Publication date: June 5, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Conte, Mario Micciche, Gianbattista Lo Giudice, Alberto Di Martino, Giampiero Sberno
  • Publication number: 20080007321
    Abstract: An integrated control circuit for a charge pump includes a first device for regulating the output voltage of the charge pump and a second device for increasing the output voltage from the charge pump with a set ramp. The integrated circuit includes means for activating said first device and providing it with a first value of a supply signal in a first period of time and for activating the second device and providing it with a second value of the supply signal that is greater than the first value in a second period of time after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value to a second value that is greater than the first value, the second value being fixed by reactivation of the first device.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 10, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Enrico CASTALDO, Antonino Conte, Gianbattista Lo Giudice
  • Patent number: 6906957
    Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: June 14, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Gianbattista Lo Giudice, Alfredo Signorello
  • Publication number: 20040057291
    Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 25, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Gianbattista Lo Giudice, Alfredo Signorello
  • Patent number: 6704233
    Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells including a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: March 9, 2004
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Antonino Conte, Gianbattista Lo Giudice, Alfredo Signorello
  • Publication number: 20020190297
    Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 19, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Gianbattista Lo Giudice, Alfredo Signorello