Abstract: An RFID transponder (T) suitable for communication with a reading device (RD) and adapted to be connected to a monitored unit (MU) is provided. The RFID transponder (T) comprises a comparing unit (CU) adapted to and arranged to receive a status signal from the monitored unit (MU) and configured to compare a value of the status signal to at least one predefined reference value and a state machine circuit (STM) connected to the comparing unit (CU) and configured to determine, based on a result of the comparison, whether the value of the status signal lies outside a range of operation defined by the at least one reference value. The state machine circuit (STM) is further configured to indicate the reading device (RD) that the value of the status signal lies outside the range of operation if the value of the status signal lies outside the range of operation.

Abstract: An RFID transponder (T) suitable for communication with a reading device (RD) and adapted to be connected to a monitored unit (MU) is provided. The RFID transponder (T) comprises a comparing unit (CU) adapted to and arranged to receive a status signal from the monitored unit (MU) and configured to compare a value of the status signal to at least one predefined reference value and a state machine circuit (STM) connected to the comparing unit (CU) and configured to determine, based on a result of the comparison, whether the value of the status signal lies outside a range of operation defined by the at least one reference value. The state machine circuit (STM) is further configured to indicate the reading device (RD) that the value of the status signal lies outside the range of operation if the value of the status signal lies outside the range of operation.

Abstract: Various exemplary embodiments relate to an integrated circuit including: a RF interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the RF interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface.

Abstract: Various exemplary embodiments relate to an integrated circuit including: a RF interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the RF interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface.

Abstract: In order to further develop a circuit arrangement (100), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being designed for carrying data signals in the form of regular data and/or in the form of the test data, the transmitted test data are received, the received test data are compared with expected test data, and any discrepancy between the received test data and the expected test data is ascertained or determined, in such way that less power is required for examining, in particular for identifying, if the circuit arrangement (100) has been attacked, it is proposed that part of the group of data lines (50) is selected to carry new or most recent test data having been generated.