Abstract: Embodiments disclosed herein may relate to forming a base contact layout in a memory device.

Abstract: Embodiments disclosed herein may relate to forming a base contact layout in a memory device.

Abstract: An integrated circuit may include lines that traverse a cross-point array, the lines fabricated at a first pitch on a first layer, wherein the first pitch is sub-lithographic, and leads on a second layer, the leads having a second pitch that is twice as large as the first pitch. The lines may be routed outside of the array in alternating groups to opposite sides of the array where the lines couple to the leads.

Abstract: An integrated circuit may include lines that traverse a cross-point array, the lines fabricated at a first pitch on a first layer, wherein the first pitch is sub-lithographic, and leads on a second layer, the leads having a second pitch that is twice as large as the first pitch. The lines may be routed outside of the array in alternating groups to opposite sides of the array where the lines couple to the leads.

Abstract: Embodiments disclosed herein may relate to forming a base contact layout in a memory device.

Abstract: A process for manufacturing an organic mask for the microelectronics industry, including forming an organic layer on a substrate; forming an inorganic mask on the organic layer; and etching selectively the organic layer through the inorganic mask. Furthermore, forming the inorganic mask includes forming at least a first auxiliary layer of a first inorganic material on the organic layer; forming a mask layer of a second inorganic material different from the first inorganic material on the first auxiliary layer; and shaping the mask layer using a dual-exposure lithographic process.

Abstract: A non-volatile memory device integrated on semiconductor substrate and having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of active areas formed on the semiconductor substrate equidistant from each other, and having at least a first and a second group of active areas; the non-volatile memory cells integrated in the first group of active areas, each non-volatile memory cell having a source region, a drain region, and a floating gate electrode coupled to a control gate electrode, at least one group of the memory cells sharing a common source region integrated on the semiconductor substrate; and a contact region integrated in the second group of active areas and provided with at least one common source contact of the common source region.