Patents by Inventor Gianfranco Ferrante
Gianfranco Ferrante has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240168889Abstract: A method includes: creating a logical-to-physical address translation (L2P) bitmap for each respective virtual block programmed across a plane of multiple dice of a memory device, each L2P bitmap identifying logical addresses, within each respective L2P table of a plurality of L2P tables, that belong to a respective virtual block; creating a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table, of the plurality of L2P tables, based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular virtual block; and identifying and updating, by the processing device, an L2P bitmap associated with the particular virtual block for an L2P mapping corresponding to the entry.Type: ApplicationFiled: January 31, 2024Publication date: May 23, 2024Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
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Patent number: 11928063Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.Type: GrantFiled: August 18, 2022Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
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Publication number: 20240061787Abstract: A method includes: creating L2P tables while programming virtual blocks (VBs) across memory planes; creating an L2P bitmap for each VB, the L2P bitmap identifying logical addresses, within each L2P table, that belong to each VB; creating a VB bitmap for each L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points; creating an updated VB bitmap for a first L2P table based on changes to the first L2P table; determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular VB; identifying an L2P bitmap corresponding to the particular VB; changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and employing the identified L2P bitmap to determine L2P table(s) of the respective L2P tables that contain valid logical addresses for the particular VB.Type: ApplicationFiled: August 18, 2022Publication date: February 22, 2024Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
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Patent number: 11768627Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.Type: GrantFiled: January 11, 2023Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
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Publication number: 20230244414Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.Type: ApplicationFiled: January 11, 2023Publication date: August 3, 2023Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
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Patent number: 11556275Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.Type: GrantFiled: May 18, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
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Publication number: 20220374163Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
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Patent number: 11461228Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.Type: GrantFiled: December 4, 2020Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventors: Gianfranco Ferrante, Dionisio Minopoli
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Publication number: 20210406169Abstract: A memory device is provided. The memory device comprises: a plurality of memory cells, each memory cell being programmable to at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the memory cell, the plurality of memory cells comprising a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of said at least two logic states; a memory controller coupled to the plurality of memory cells and configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation to assess the logic state thereof.Type: ApplicationFiled: October 9, 2019Publication date: December 30, 2021Inventors: Dionisio Minopoli, Daniele Balluchi, Gianfranco Ferrante
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Patent number: 11132311Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: GrantFiled: December 4, 2019Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Publication number: 20210089443Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Inventors: Gianfranco Ferrante, Dionisio Minopoli
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Patent number: 10860474Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.Type: GrantFiled: December 14, 2017Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventors: Gianfranco Ferrante, Dionisio Minopoli
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Publication number: 20200104268Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Patent number: 10534731Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: GrantFiled: March 19, 2018Date of Patent: January 14, 2020Assignee: Micron Technology, Inc.Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Publication number: 20190286586Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: ApplicationFiled: March 19, 2018Publication date: September 19, 2019Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Publication number: 20190188124Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.Type: ApplicationFiled: December 14, 2017Publication date: June 20, 2019Inventors: Gianfranco Ferrante, Dionisio Minopoli
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Patent number: 10175908Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data. The controller identifies the association of the one or more blocks of data with the file and executes the one or more commands, such that the one or more blocks of data are stored in the memory device with a placement based upon the association.Type: GrantFiled: January 4, 2018Date of Patent: January 8, 2019Assignee: Micron Technology, Inc.Inventors: Danilo Caraccio, Graziano Mirichigni, Gianfranco Santopietro, Gianfranco Ferrante, Emanuele Confalonieri
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Publication number: 20180129442Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data.Type: ApplicationFiled: January 4, 2018Publication date: May 10, 2018Inventors: Danilo Caraccio, Graziano Mirichigni, Gianfranco Santopietro, Gianfranco Ferrante, Emanuele Confalonieri
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Patent number: 9880772Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.Type: GrantFiled: September 21, 2015Date of Patent: January 30, 2018Assignee: Micron Technology, Inc.Inventors: Danilo Caraccio, Graziano Mirichigni, Gianfranco Santopietro, Gianfranco Ferrante, Emanuele Confalonieri
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Publication number: 20170083260Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.Type: ApplicationFiled: September 21, 2015Publication date: March 23, 2017Inventors: Danilo Caraccio, Graziano Mirichigni, Gianfranco Santopietro, Gianfranco Ferrante, Emanuele Confalonieri