Patents by Inventor Giang Dao
Giang Dao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20050235135Abstract: An electronic system that includes control logic that causes input and output ports to be disabled during the interruption windows of the initialization process, and subsequently to be selectively disabled or enabled after completion of the initialization process. The input and output ports are disabled during initialization of the electronic system to prevent interruption of the initialization process by the user. The input and output ports are disabled or enabled, after completion of the initialization process, to control access to content stored on, or made available by, the electronic system.Type: ApplicationFiled: April 16, 2004Publication date: October 20, 2005Applicant: Eagle Broadband, Inc.Inventors: Giang Dao, Jonathan Hayden, Harold Vang
-
Patent number: 6793717Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.Type: GrantFiled: June 11, 2003Date of Patent: September 21, 2004Assignee: Intel CorporationInventors: Han-Ming Wu, Giang Dao
-
Patent number: 6734443Abstract: A method and apparatus to remove contamination and control electrostatic discharge in-situ in a semiconductor device manufacture process. In an embodiment, the method includes providing a reticle having first and second planar surfaces into a chamber. A circuit pattern of opaque material may be disposed on the first planar surface of the reticle. The method further includes irradiating the reticle using an ultraviolet light radiation beam to remove contamination disposed on the first and second planar surfaces of the reticle and to neutralize static electricity accumulated by the reticle.Type: GrantFiled: May 8, 2001Date of Patent: May 11, 2004Assignee: Intel CorporationInventors: Jun Fei Zheng, Giang Dao
-
Publication number: 20040045433Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.Type: ApplicationFiled: June 11, 2003Publication date: March 11, 2004Inventors: Han-Ming Wu, Giang Dao
-
Patent number: 6660649Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness. The present invention also describes a mask comprising: an absorber layer, the absorber layer having a first opening and a second opening, the first opening uncovering a balancing layer disposed over a substrate having a first thickness, and the second opening uncovering the substrate having a second thickness.Type: GrantFiled: August 29, 2002Date of Patent: December 9, 2003Assignee: Intel CorporationInventors: Giang Dao, Qi-De Qian
-
Patent number: 6625800Abstract: A method is described that involves accepting a mask design file input and then simulating the inspection of a mask through an optical channel. The mask design file has patterns. The optical channel corresponds to a mask inspection tool optical channel. The mask is patterned according to the mask design file patterns.Type: GrantFiled: December 30, 1999Date of Patent: September 23, 2003Assignee: Intel CorporationInventors: Qi-De Qian, Edita Tejnil, Giang Dao
-
Patent number: 6610123Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.Type: GrantFiled: December 17, 2001Date of Patent: August 26, 2003Assignee: Intel CorporationInventors: Han-Ming Wu, Giang Dao
-
Patent number: 6611327Abstract: Testing of a mask which is intended to be used for low wavelength lithography. At lower wavelengths, e.g., 157 nm, certain contaminants may become visible, even though they were transparent under visible or ultraviolet light. A combination of Raman spectroscopy and infrared absorption spectroscopy are used to identify the contaminants.Type: GrantFiled: March 23, 2001Date of Patent: August 26, 2003Assignee: Intel CorporationInventors: Arun Ramamoorthy, Giang Dao, Christopher Gerth
-
Publication number: 20030110944Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.Type: ApplicationFiled: December 17, 2001Publication date: June 19, 2003Inventors: Han-Ming Wu, Giang Dao
-
Patent number: 6548417Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness. The present invention also describes a mask comprising: an absorber layers the absorber layer having a first opening and a second opening, the first opening uncovering a balancing layer disposed over a substrate having a first thickness, and the second opening uncovering the substrate having a second thickness.Type: GrantFiled: September 19, 2001Date of Patent: April 15, 2003Assignee: Intel CorporationInventors: Giang Dao, Qi-De Qian
-
Patent number: 6537706Abstract: A method for making a photolithographic mask. The method comprises forming a film on a substrate that deforms the substrate, and applying a deformation reducing agent to the substrate to reduce the amount of deformation that the film caused. In a preferred embodiment, the deformation reducing agent comprises one or more films, which are formed on one side of the substrate, that balance the substrate deformation effect of one or more films that are deposited on the other side of the substrate. The film or films that constitute the deformation reducing agent may be similar to, or different from, an absorption film and/or any other films deposited on the substrate or on the absorption film.Type: GrantFiled: March 14, 2000Date of Patent: March 25, 2003Assignee: Intel CorporationInventors: Qing Ma, Jin Lee, Jun Fei Zheng, Giang Dao
-
Publication number: 20030054260Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness.Type: ApplicationFiled: September 19, 2001Publication date: March 20, 2003Inventors: Giang Dao, Qi-De Qian
-
Publication number: 20030054262Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness.Type: ApplicationFiled: August 29, 2002Publication date: March 20, 2003Inventors: Giang Dao, Qi-De Qian
-
Publication number: 20020179852Abstract: A method and apparatus to remove contamination and control electrostatic discharge in-situ in a semiconductor device manufacture process. In an embodiment, the method includes providing a reticle having first and second planar surfaces into a chamber. A circuit pattern of opaque material may be disposed on the first planar surface of the reticle. The method further includes irradiating the reticle using an ultraviolet light radiation beam to remove contamination disposed on the first and second planar surfaces of the reticle and to neutralize static electricity accumulated by the reticle.Type: ApplicationFiled: May 8, 2001Publication date: December 5, 2002Inventors: Jun Fei Zheng, Giang Dao.
-
Publication number: 20020135759Abstract: Testing of a mask which is intended to be used for low wavelength lithography. At lower wavelengths, e.g., 157 nm, certain contaminants may become visible, even though they were transparent under visible or ultraviolet light. A combination of Raman spectroscopy and infrared absorption spectroscopy are used to identify the contaminants.Type: ApplicationFiled: March 23, 2001Publication date: September 26, 2002Inventors: Arun Ramamoorthy, Giang Dao, Christopher Gerth