Abstract: A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language includes a repository (10) storing a general set of self-checking tests applicable to the integrated circuits. A capability is provided for entering behavior data (21) of an integrated circuit model (20), and for entering configuration data (22) of the integrated circuit model. The generator automatically generates test benches (30) in the Hardware Description Language by making a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behavior data.

Abstract: A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines. The managing logic includes a control block for generating a first enable signal of the precharge step and a second enable signal of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.

Abstract: The semi-conductor memory includes a memory device to store digital data being provided with a first number of intermediate output ports including a first intermediate output port. Furthermore, the memory includes a register block that can be selectively connected to the first intermediate output port to store data in the memory device and a second number of output ports including first and second output ports. The memory includes an interface device to receive strobe signals from the memory device, each being indicative of the presence of data on the at least one intermediate output port. This interface device, based on the strobe signals, controls the register block to provide the data stored in the register on the first and second output ports, by emulating a multi-port memory where the second number is greater than the first number.

Abstract: A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines. The managing logic includes a control block for generating a first enable signal of the precharge step and a second enable signal of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.

Abstract: The semi-conductor memory includes a memory device to store digital data being provided with a first number of intermediate output ports including a first intermediate output port. Furthermore, the memory includes a register block that can be selectively connected to the first intermediate output port to store data in the memory device and a second number of output ports including first and second output ports. The memory includes an interface device to receive strobe signals from the memory device, each being indicative of the presence of data on the at least one intermediate output port. This interface device, based on the strobe signals, controls the register block to provide the data stored in the register on the first and second output ports, by emulating a multi-port memory where the second number is greater than the first number.

Abstract: A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language includes a repository (10) storing a general set of self-checking tests applicable to the integrated circuits. A capability is provided for entering behavior data (21) of an integrated circuit model (20), and for entering configuration data (22) of the integrated circuit model. The generator automatically generates test benches (30) in said Hardware Description Language by making a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behavior data.

Abstract: A memory circuit having a first and a second block of memory cells with rows that cross both blocks and columns in each of the two blocks. A word decoder selects one of the rows, and a column decoder selects a set of columns from the first and second blocks. An address splitter passes relative portions of an address to each decoder. In one embodiment, the address splitter passes the most significant bits of the address to the word decoder and passes the remaining bits to a portion of the column decoder coupled to the first block only. The address splitter also modifies the remaining bits, using a bit subtractor, and passes them to a portion of the column decoder coupled to the second block only. A method of operating a memory device is provided that includes accepting an address at an input address circuit and then determining whether the address is for data in the first block or in the second block. This information is assessed by comparing it to the number of memory cells in the first block.