Patents by Inventor Gianluca Scalisi

Gianluca Scalisi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11763908
    Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
  • Patent number: 11495317
    Abstract: A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Vigilante, Gianluca Scalisi
  • Publication number: 20220101938
    Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
  • Patent number: 11211136
    Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
  • Publication number: 20200411129
    Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Andrea Vigilante, Gianluca Scalisi, Andrea Pozzato, Andrea Salvioni, Mauro Luigi Sali
  • Publication number: 20200411127
    Abstract: A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Andrea Vigilante, Gianluca Scalisi