Abstract: An integrated circuit includes a sequential logic circuit and a circuit configured to change operation as a function of state output signals provided by state flip-flops of the sequential logic circuit. With a test mode signal asserted, a test circuit writes and reads the content of the state flip-flops in order to test the operation of the sequential logic circuit. A processing system includes at least one storage circuit interposed between the circuit and a respective state output signal. Each storage circuit receives the respective state output signal and provides a modified state signal to the circuit. When the test mode signal is de-asserted, the storage circuit provides the received state output signal in a transparent manner to the circuit and stores the received state output signal to a storage element. When the test mode signal is asserted, the storage circuit provides the stored state output signal to the circuit.

Abstract: A processing system includes configuration registers and a non-volatile memory with memory slots storing configuration data bits and error detection bits. A hardware configuration circuit sequentially reads the data bits from the non-volatile memory for storage in respective configuration registers by: receiving bits from a current memory slot; selectively asserting an error signal in response to comparison of received error detection bits with calculated error detection bits; storing the received bits to temporary registers where the error signal deasserted and other otherwise asserting a further error signal where the error signal is asserted. Otherwise, predetermined configuration data is stored to the temporary registers. The content of the temporary registers is then sequentially stored to the configuration registers. A reset signal is generated in response to the further error signal to reset the configuration registers.