Abstract: Presented is a process for manufacturing virtual ground electronic memory devices integrated in a semiconductor having a conductivity of a first type and having at least one matrix of floating gate memory cells. In the matrix there are a number of continuous bit lines extending across the substrate as discrete parallel strips, and a number of word lines extending in a transverse direction to the bit lines. The method begins by forming gate regions of the memory cells to produce a number of continuous strips seperated by parallel openings. Then, a dopant is implanted to form, within the parallel openings, the bit lines with conductivity of a second type. Spacers are formed on sidewalls of the gate regions. Then a first layer of a transition metal is deposited into said parallel openings, and the transition metal layer is subjected to a thermal treatment for reacting it with semiconductor substract and forming a silicide layer over the bit lines.