Patents by Inventor Gianni Michele Nannetti

Gianni Michele Nannetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030056084
    Abstract: There is provided an object orientated heterogeneous multi-processor architecture comprising a plurality of execution units amongst which object methods are distributed, a run-time support, a shared memory for storing object data and which is accessible by the execution units and by the run-time support, and an invocation network for carrying method invocation messages between execution units and/or between the run-time support. Object based source code is distributable across a variable number of the execution units. The invocation network is logically distinct from any mechanism for accessing the object data stored in the shared memory. Also provided are methods of operating the heterogeneous multi-processor architecture and of managing communications in an object orientated program execution environment.
    Type: Application
    Filed: August 19, 2002
    Publication date: March 20, 2003
    Inventors: Christopher John Holgate, Gianni Michele Nannetti, Hugh Alexander Prosser Eland, Paul David Onions, Franklin Charles Wray, Tirumala Rao Parvataneni
  • Patent number: 6122690
    Abstract: A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus interface for either a bus master functional block or a slave functional block. Each bus interface includes a state machine that has at least two operational modes including a fast operational mode having two states and a normal operational mode having at least four states. A bus interface coupled to a bus master functional block implements an operational mode and a bus interface coupled to a slave functional block operates in a complementary operational mode. Each bus interface is also equipped to facilitate scaling of the address and/or data width on the bus.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: September 19, 2000
    Assignee: Mentor Graphics Corporation
    Inventors: Gianni Michele Nannetti, Tirumal Rao Parvataneni