Abstract: Variable frequency oscillators allowing wide tuning range and low phase noise is disclosed. In an illustrative embodiment, a first transistor has a first terminal (e.g. collector) connected to a reference voltage, and a second terminal (e.g. emitter) connected to a first terminal of a first current source and to ground. The first transistor further has a third terminal connected to a first inductor and to a first capacitor connected to the emitter of the first transistor and also to a second capacitor connected to ground. A second transistor is similarly constructed. In order to achieve a variable frequency oscillation between the emitters of the two transistors, a variable tank capacitor is connected between the inductors, forming a circuit connecting in series all passive components composing the LC tank, masking most of parasitic capacitances.

Abstract: A multiloop PLL circuit comprising: a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO; at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R1) and a third (N1) programmable dividers, and a second loop filter a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer whereby the desired output frequency Fout is generated in accordance with the relation: Fout=(N1/R1+

Abstract: A variable frequency oscillator comprising a first transistor (10) and a second transistor (20); wherein the first transistor (10) has a first terminal—collector—which is connected to a reference voltage, and a second terminal—emitter—which is connected to a first terminal of a first current source (13), which second terminal is connected to ground, and a third terminal—base—connected to a first terminal of a first inductor (14) and to a top terminal of a first capacitor (11), wherein the first capacitor (11) has a bottom terminal which is connected to the second terminal—emitter—of the first transistor (10) but also to a top terminal of a second capacitor (12) having a bottom terminal being connected to ground; wherein the second transistor (20) has a first terminal—collector—which is connected to a reference voltage, and a second terminal—emitter—which is connected to a first terminal of a second current source (23), which second terminal is connected to ground, and a third terminal—base—connected to a f

Abstract: A multiloop PLL circuit comprising: a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO; at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R1) and a third (N1) programmable dividers, and a second loop filter a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer whereby the desired output frequency Fout is generated in accordance with the relation: Fout=(N

Abstract: A tunable multiple frequency source system employing offset signal phasing includes a first frequency source, a phase delay element, and a second frequency source configured to operate concurrently with the first frequency source. The first frequency source includes an input coupled to receive a reference input signal and an output for providing a first frequency source signal. The phase delay includes an input coupled to receive the input reference signal, and an output, the phase delay element operable to apply a predefined phase delay to the input reference signal to produce a phase-delayed input signal. The second frequency source includes an input coupled to receive the phase-delayed input signal and an output for providing a second frequency source signal.

Abstract: A multiple frequency source system includes at least one frequency source tunable to a predefined target frequency, and at least one additional frequency source operable to generate a second signal at a frequency which is either higher or lower than the target frequency. A method for tuning the tunable frequency source to the target frequency during concurrent generation of the second signal includes (i) controlling the tunable frequency source to tune to at least one frequency point frequency lower than the target frequency, and thereafter controlling the oscillator to tune to the target frequency, when the second signal is higher in frequency than the target frequency, or (ii) controlling the tunable frequency source to tune to at least one frequency point higher than the target frequency, and thereafter controlling the tunable frequency source to tune to the target frequency, when the second signal is lower in frequency than the target frequency.

Abstract: A method for mitigating phase pulling in multiple frequency source system includes generating a first signal, the first signal referred to as an existing signal operating at an existing frequency point, the existing signal having a predefined pulling bandwidth around the existing frequency point. A request is received to generate a prospective signal at a prospective frequency point which is within the predefined pulling bandwidth of the existing signal. The prospective frequency is removed from within the predefined pulling bandwidth, and the prospective and existing signals are generated at the corresponding frequency points.

Abstract: A tuning circuit uses a VCO with a trimming capacitor bank. The trimming capacitor bank is calibrated by logic to accommodate a desired frequency, fwanted. A search renders an initial control word that is accurate within one LSB. In a first embodiment, comparisons between the desired frequency and the upper and lower frequency bounds of the VCO with the trimming capacitor bank configured by the initial control word. The control word may be increased or decreased based on the comparisons. In a second embodiment, differences between the desired frequency and the actual frequency of the VCO, with the trimming capacitor bank configured by the initial control word, are compared to a threshold. The control word may be increased or decreased based on the comparison.

Abstract: A method for mitigating phase pulling in multiple frequency source system includes generating a first signal, the first signal referred to as an existing signal operating at an existing frequency point, the existing signal having a predefined pulling bandwidth around the existing frequency point. A request is received to generate a prospective signal at a prospective frequency point which is within the predefined pulling bandwidth of the existing signal. The prospective frequency is removed from within the predefined pulling bandwidth, and the prospective and existing signals are generated at the corresponding frequency points.

Abstract: A multiple frequency source system includes at least one frequency source tunable to a predefined target frequency, and at least one additional frequency source operable to generate a second signal at a frequency which is either higher or lower than the target frequency. A method for tuning the tunable frequency source to the target frequency during concurrent generation of the second signal includes (i) controlling the tunable frequency source to tune to at least one frequency point frequency lower than the target frequency, and thereafter controlling the oscillator to tune to the target frequency, when the second signal is higher in frequency than the target frequency, or (ii) controlling the tunable frequency source to tune to at least one frequency point higher than the target frequency, and thereafter controlling the tunable frequency source to tune to the target frequency, when the second signal is lower in frequency than the target frequency.

Abstract: A tunable multiple frequency source system employing offset signal phasing includes a first frequency source, a phase delay element, and a second frequency source configured to operate concurrently with the first frequency source. The first frequency source includes an input coupled to receive a reference input signal and an output for providing a first frequency source signal. The phase delay includes an input coupled to receive the input reference signal, and an output, the phase delay element operable to apply a predefined phase delay to the input reference signal to produce a phase-delayed input signal. The second frequency source includes an input coupled to receive the phase-delayed input signal and an output for providing a second frequency source signal.

Abstract: A phase lock loop circuit 60 has a phase frequency detector 62, a charge pump 64, an active filter 87 and a voltage-controlled oscillator 100. The phase detector generates UP and DN signals indicative of the relative frequency of FR, a reference signal, and FV, a signal controlled by the voltage-controlled oscillator. A charge pump using logic gates (buffer 66 and inverter 68) to produce a voltage drop over resistors 74 and 84 to generate a voltage at a node coupled to the input of transmission gate 76 according to the values of the UP and DN signals. When the transmission gate 76 is closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier 86 of the active filter 86. When the transmission gate is open (high impedance state) the inverting input is electrically isolated from the node.

Abstract: A phase lock loop circuit (60) has a phase frequency detector (62), a charge pump (64), an active filter (87) and a voltage-controlled oscillator (100). The phase detector generates signals responsive to reference signal FR and VCO output signal FV. A charge pump generates a voltage at the input of a first transmission gate (76) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate (112). When the transmission gates (76, 110) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier (86) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.

Abstract: A phase lock loop circuit (60) has a phase frequency detector (62), a charge pump (64), an active filter (87) and a voltage-controlled oscillator (100). The phase detector generates signals responsive to reference signal FR and VCO output signal FV. A charge pump generates a voltage at the input of a first transmission gate (76) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate (112). When the transmission gates (76, 110) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier (86) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.

Abstract: A tuning circuit uses a VCO with a trimming capacitor bank. The trimming capacitor bank is calibrated by logic to accommodate a desired frequency, fwanted. A search renders an initial control word that is accurate within one LSB. In a first embodiment, comparisons between the desired frequency and the upper and lower frequency bounds of the VCO with the trimming capacitor bank configured by the initial control word. The control word may be increased or decreased based on the comparisons. In a second embodiment, differences between the desired frequency and the actual frequency of the VCO, with the trimming capacitor bank configured by the initial control word, are compared to a threshold. The control word may be increased or decreased based on the comparison.

Abstract: A phase lock loop circuit 60 has a phase frequency detector 62, a charge pump 64, an active filter 87 and a voltage-controlled oscillator 100. The phase detector generates UP and DN signals indicative of the relative frequency of FR, a reference signal, and FV, a signal controlled by the voltage-controlled oscillator. A charge pump using logic gates (buffer 66 and inverter 68) to produce a voltage drop over resistors 74 and 84 to generate a voltage at a node coupled to the input of transmission gate 76 according to the values of the UP and DN signals. When the transmission gate 76 is closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier 86 of the active filter 86. When the transmission gate is open (high impedance state) the inverting input is electrically isolated from the node.