Abstract: Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and Bit nodes of a bit cell prior to a write operation. Equalization may be performed with a pulse-controlled transistor to transfer charge between the storage nodes. Pulse width and/or amplitude may be configurable, such as to scale with voltage. Bit cell write-assist may include reduction of bit cell retention strength during equalization, which may be continued during a write operation. Write-assist may be provided to each of multiple bit cells when a write operation is directed to a subset of the bit cells, which may conserve power and/or area. A partially-decoded address may be used to provide write-assistance to multiple bit cells prior to a write operation. Write-assistance may permit writing of Bit and Bit with a voltage swing significantly lower than an operating voltage of the bit cell.

Abstract: Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and Bit nodes of a bit cell prior to a write operation. Equalization may be performed with a pulse-controlled transistor to transfer charge between the storage nodes. Pulse width and/or amplitude may be configurable, such as to scale with voltage. Bit cell write-assist may include reduction of bit cell retention strength during equalization, which may be continued during a write operation. Write-assist may be provided to each of multiple bit cells when a write operation is directed to a subset of the bit cells, which may conserve power and/or area. A partially-decoded address may be used to provide write-assistance to multiple bit cells prior to a write operation. Write-assistance may permit writing of Bit and Bit with a voltage swing significantly lower than an operating voltage of the bit cell.

Abstract: A method and apparatus for a multi-purpose adder is described. The method includes calculation of an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal. Generation of an initial carryout signal for each calculated initial sum is then performed. Next, an intermediate sum for each group of M-initial sums according to a respective initial carryout value of each initial sum is then generated. Once generated, an intermediate carryout value for each generated intermediate sum is then calculated. Finally, a final sum is calculated from the intermediate sums generated according to a respective intermediate carryout of each intermediate sum.

Abstract: A method and apparatus for a multi-purpose adder is described. The method includes calculation of an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal. Generation of an initial carryout signal for each calculated initial sum is then performed. Next, an intermediate sum for each group of M-initial sums according to a respective initial carryout value of each initial sum is then generated. Once generated, an intermediate carryout value for each generated intermediate sum is then calculated. Finally, a final sum is calculated from the intermediate sums generated according to a respective intermediate carryout of each intermediate sum.

Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A method for retransmitting selected data elements read from a memory. A first sequence of individually addressable data elements d.sub.1, d.sub.2, . . . , d.sub.n are read from the memory. First and second signals indicate whether each data element was read without or with, respectively, a transmission error. A second sequence of data elements d.sub.i, d.sub.i+1, . . . , d.sub.n, where d.sub.i is the first data element of the first sequence to have a transmission error is then retransmitted.

Abstract: A method and apparatus for measuring threshold voltages associated with the EEPROM portion of a non-volatile DRAM (NVDRAM) memory cell. The DRAM node of the NVDRUM cell is charged to a high potential and allowed to discharge through the EEPROM transistor. Since the gate of the EEPROM is tied to the DRAM node, the DRAM node voltage, which is also the EEPROM gate-to-source voltage, will, if the NVDRAM is left alone, drop until the EEPROM transistor shuts off. The EEPROM gate-to-source voltage at any point in time along this discharge path is measured through an iterative process. First, timing signals are adjusted to specify the point in time at which the EEPROM voltage is to be measured. Then, during each iteration, the EEPROM voltage is charged up and allowed to the discharge. At the point in time along the discharge path specified by the timing signals, a reference voltage is compared with the EEPROM voltage to determine if the reference voltage is above or below the EEPROM voltage.

Abstract: In a non-volatile DRAM (NVDRAM) memory device comprised of NVDRAM cells, each comprising a DRAM cell and an EEPROM cell, a method and apparatus for the page recall of data whereby the page recall start address may be specified by the user through the memory device's external control pins. A page of memory cells is defined as all of the memory cells connected to a single word line. During any recall operation, data are recalled from EEPROM to DRAM in only one memory cell per bit line. The externally specified page recall start address is input onto an external pad. It is then transmitted through an address selector circuit into the inputs of a counter circuit. The outputs of the counter circuit serve as the page recall start address, which reenters the address selector circuitry to be transmitted to address decoding circuitry.

Abstract: A circuit for generating clock and control signals from first and second asynchronous binary signals. The circuit generates first and second pulse signals responsive to the first and second asynchronous binary signals, a clock pulse signal responsive to the first or second pulse signal, and an identification control signal to indicate which of the two binary signals is responsible for the clock signal. The circuit is also responsive to the first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.

Abstract: A sense amplifier for a read only memory array which is formed from a multiplicity of NAND organized FET stacks. The sense amplifier compares the current sinking capacity of a selected bit line stack with that of a reference stackline, the difference being detected as a voltage shift in a differential stage. Pass FETs with gate electrodes biased in inverse proportion to the bit and reference line potentials are serially connected between the corresponding lines and reference nodes.

Abstract: A field effect transistor driver circuit figured to have different rates of change of the output signal depending on fabrication mask designation of selected transistors to be either depletion or enhancement type devices.

Abstract: A read-only memory array formed from a multiplicity of NAND-organized FET stacks which are arranged in pairs and connected in alternate succession of adjacent pairs at opposite ends. Selection of stacks by pairs is performed by connecting the common node of four stacks at one end to a bit line and the common node of another four stacks, only two being common with the former four stacks, to ground potential. Selection between adjacent stack pairs is performed by bank select FETs in each stack. Each stack is precharged at both ends prior to selection. A sense amp is utilized to compare the current sinking capacity of the selected bit line with a reference stack, the difference being detected in a differential amplifier. A programmable output driver provides an adjustable rate of change in the output signal for step input signals.