Patents by Inventor Gideon D. Intrater
Gideon D. Intrater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120221838Abstract: The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register.Type: ApplicationFiled: February 24, 2012Publication date: August 30, 2012Applicant: MIPS Technologies, Inc.Inventors: Soumya BANERJEE, Gideon D. INTRATER, Michael Gottlieb JENSEN
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Patent number: 8151093Abstract: The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in architectural state from occurring as a result of execution of a specific sequence of instruction types. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor.Type: GrantFiled: September 8, 2006Date of Patent: April 3, 2012Assignee: MIPS Technologies, Inc.Inventors: Soumya Banerjee, Gideon D. Intrater, Michael Gottlieb Jensen
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Patent number: 7634619Abstract: A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing. If the access is redirected, the access to the instruction memory is performed by the instruction memory interface, and data retrieved by the instruction memory interface is then provided to the data memory interface, and in turn to the pipeline stage that requested the data memory interface to access the data.Type: GrantFiled: August 29, 2005Date of Patent: December 15, 2009Assignee: MIPS Technologies, Inc.Inventors: Gideon D. Intrater, Anders M. Jagd, Ryan C. Kinter
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Patent number: 7509456Abstract: The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.Type: GrantFiled: December 3, 2004Date of Patent: March 24, 2009Assignee: MIPS Technologies, Inc.Inventors: Ryan C. Kinter, Scott M. McCoy, Gideon D. Intrater
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Publication number: 20080065868Abstract: The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in architectural state from occurring as a result of execution of a specific sequence of instruction types. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor.Type: ApplicationFiled: September 8, 2006Publication date: March 13, 2008Applicant: MIPS Technologies, Inc.Inventors: Soumya Banerjee, Gideon D. Intrater, Michael Gottlieb Jensen
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Patent number: 6961819Abstract: A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing.Type: GrantFiled: April 26, 2002Date of Patent: November 1, 2005Assignee: MIPS Technologies, Inc.Inventors: Gideon D. Intrater, Anders M. Jagd, Ryan C. Kinter
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Patent number: 6836833Abstract: The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configurations of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.Type: GrantFiled: October 22, 2002Date of Patent: December 28, 2004Assignee: MIPS Technologies, Inc.Inventors: Ryan C. Kinter, Scott M. McCoy, Gideon D. Intrater
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Publication number: 20030204685Abstract: A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing. If the access is redirected, the access to the instruction memory is performed by the instruction memory interface, and data retrieved by the instruction memory interface is then provided to the data memory interface, and in turn to the pipeline stage within the processing system that requested the data memory interface to access the data.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Applicant: MIPS Technologies, Inc.Inventors: Gideon D. Intrater, Anders M. Jagd, Ryan C. Kinter