Patents by Inventor Gideon Intrater
Gideon Intrater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11704258Abstract: A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.Type: GrantFiled: August 11, 2021Date of Patent: July 18, 2023Assignee: Dialog Semiconductor US Inc.Inventor: Gideon Intrater
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Patent number: 11681352Abstract: A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.Type: GrantFiled: September 28, 2020Date of Patent: June 20, 2023Assignee: Adesto Technologies CorporationInventor: Gideon Intrater
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Publication number: 20230131586Abstract: A memory device, can include: a control circuit configured to operate the memory device in one of an active mode, a standby mode, and a sleep mode, where the memory device is configured to receive a command from a host device when in the standby mode; a voltage regulator having an output that provides a supply voltage for accessing contents of memory cells in the memory device, where the voltage regulator is off during the sleep mode and the standby mode, and the voltage regulator is on during the active mode; and a storage element configured to maintain the supply voltage to allow the voltage regulator to be turned off during the standby mode, and at least until the voltage regulator turns on in the active mode and supports the supply voltage.Type: ApplicationFiled: October 26, 2021Publication date: April 27, 2023Inventors: Bard M. Pedersen, Gideon Intrater
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Publication number: 20230050986Abstract: A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.Type: ApplicationFiled: August 11, 2021Publication date: February 16, 2023Inventor: Gideon Intrater
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Patent number: 11366774Abstract: A method of controlling a read request can include: receiving, in a host device, the read request from a bus master, where the host device is coupled to a memory device by an interface; determining a configuration state of the read request; comparing an attribute of the read request against a predetermined attribute stored in the host device; adjusting the configuration state of the read request when the attribute of the read request matches the predetermined attribute; and sending the read request with the adjusted configuration state from the host device to the memory device via the interface.Type: GrantFiled: September 24, 2020Date of Patent: June 21, 2022Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen
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Publication number: 20220092004Abstract: A method of controlling a read request can include: receiving, in a host device, the read request from a bus master, where the host device is coupled to a memory device by an interface; determining a configuration state of the read request; comparing an attribute of the read request against a predetermined attribute stored in the host device; adjusting the configuration state of the read request when the attribute of the read request matches the predetermined attribute; and sending the read request with the adjusted configuration state from the host device to the memory device via the interface.Type: ApplicationFiled: September 24, 2020Publication date: March 24, 2022Inventors: Gideon Intrater, Bard Pedersen
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Patent number: 11094375Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: GrantFiled: March 3, 2020Date of Patent: August 17, 2021Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Publication number: 20210157389Abstract: A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.Type: ApplicationFiled: September 28, 2020Publication date: May 27, 2021Inventor: Gideon Intrater
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Patent number: 10726888Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.Type: GrantFiled: March 12, 2019Date of Patent: July 28, 2020Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Ishai Naveh
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Publication number: 20200202924Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: ApplicationFiled: March 3, 2020Publication date: June 25, 2020Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Patent number: 10636480Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: GrantFiled: May 2, 2016Date of Patent: April 28, 2020Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Patent number: 10613763Abstract: A memory device can include: a memory array arranged to store data lines; an interface that receives a first read command requesting bytes of data in a consecutively addressed order from a starting byte; a cache memory having a first buffer storing a first data line including the starting byte, and a second buffer storing a second data line, from the cache memory or the memory array; output circuitry that accesses data from the first buffer, and sequentially outputs each byte from the starting byte through a highest addressed byte of the first data line; and from the second buffer and sequentially outputs each byte from a lowest addressed byte of the second data line until the requested bytes of data have been output in order to execute the first read command, the contents of the first and second buffers being maintained in the cache memory.Type: GrantFiled: March 21, 2017Date of Patent: April 7, 2020Assignee: Adesto Technologies CorporationInventor: Gideon Intrater
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Patent number: 10509589Abstract: A method of controlling a memory device can include: (i) receiving a first read command for a critical byte, where the critical byte resides in a first group of a memory array on the memory device; (ii) reading the critical byte from the memory array in response to the first read command, and providing the critical byte; (iii) reading a next byte in the first group; (iv) outputting the next byte from the first group when a clock pulse; (v) repeating the reading the next byte and the outputting the next byte for each byte in the first group; (vi) reading a first byte in a second group of the memory array, where the second group is sequential to the first group, and where each group is allocated to a cache line; and (vii) outputting the first byte from the second group when a clock pulse is received.Type: GrantFiled: August 13, 2015Date of Patent: December 17, 2019Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen
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Patent number: 10409505Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.Type: GrantFiled: April 13, 2016Date of Patent: September 10, 2019Assignee: Adesto Technologies CorporationInventors: Derric Lewis, John Dinh, Gideon Intrater, Nathan Gonzales
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Publication number: 20190237118Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.Type: ApplicationFiled: March 12, 2019Publication date: August 1, 2019Inventors: Gideon Intrater, Bard Pedersen, Ishai Naveh
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Patent number: 10290334Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.Type: GrantFiled: September 29, 2017Date of Patent: May 14, 2019Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Ishai Naveh
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Patent number: 10275372Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.Type: GrantFiled: June 18, 2018Date of Patent: April 30, 2019Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Paul Hill
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Patent number: 10031869Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.Type: GrantFiled: March 23, 2015Date of Patent: July 24, 2018Assignee: Adesto Technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Paul Hill
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Publication number: 20180166130Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.Type: ApplicationFiled: May 2, 2016Publication date: June 14, 2018Applicant: Adesto technologies CorporationInventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
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Publication number: 20180150252Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.Type: ApplicationFiled: April 13, 2016Publication date: May 31, 2018Inventors: Derric Lewis, John Dinh, Gideon Intrater, Nathan Gonzales