Patents by Inventor Gideon Levinsky
Gideon Levinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11914511Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.Type: GrantFiled: June 22, 2020Date of Patent: February 27, 2024Assignee: Apple Inc.Inventors: Francesco Spadini, Gideon Levinsky, Mridul Agarwal
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Publication number: 20210397555Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.Type: ApplicationFiled: June 22, 2020Publication date: December 23, 2021Inventors: Francesco Spadini, Gideon Levinsky, Mridul Agarwal
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Patent number: 10831675Abstract: A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality of memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.Type: GrantFiled: April 5, 2019Date of Patent: November 10, 2020Assignee: Oracle International CorporationInventors: John Pape, Manish Shah, Gideon Levinsky, Jared Smolens
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Patent number: 10430342Abstract: An apparatus includes a buffer configured to store a plurality of instructions previously fetched from a memory, wherein each instruction of the plurality of instructions may be included in a respective thread of a plurality of threads. The apparatus also includes control circuitry configured to select a given thread of the plurality of threads dependent upon a number of instructions in the buffer that are included in the given thread. The control circuitry is also configured to fetch a respective instruction corresponding to the given thread from the memory, and to store the respective instruction in the buffer.Type: GrantFiled: November 18, 2015Date of Patent: October 1, 2019Assignee: Oracle International CorporationInventors: Yuan Chou, Gideon Levinsky, Manish Shah, Robert Golla, Matthew Smittle
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Publication number: 20190236027Abstract: A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality of memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.Type: ApplicationFiled: April 5, 2019Publication date: August 1, 2019Inventors: John Pape, Manish Shah, Gideon Levinsky, Jared Smolens
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Patent number: 10331567Abstract: A prefetch circuit may include a memory, each entry of which may store an address and other prefetch data used to generate prefetch requests. For each entry, there may be at least one “quality factor” (QF) that may control prefetch request generation for that entry. A global quality factor (GQF) may control generation of prefetch requests across the plurality of entries. The prefetch circuit may include one or more additional prefetch mechanisms. For example, a stride-based prefetch circuit may be included that may generate prefetch requests for strided access patterns having strides larger than a certain stride size. Another example is a spatial memory streaming (SMS)-based mechanism in which prefetch data from multiple evictions from the memory in the prefetch circuit is captured and used for SMS prefetching based on how well the prefetch data appears to match a spatial memory streaming pattern.Type: GrantFiled: February 17, 2017Date of Patent: June 25, 2019Assignee: Apple Inc.Inventors: Stephan G. Meier, Tyler J. Huberty, Nikhil Gupta, Francesco Spadini, Gideon Levinsky
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Patent number: 10255197Abstract: A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.Type: GrantFiled: July 20, 2016Date of Patent: April 9, 2019Assignee: Oracle International CorporationInventors: John Pape, Manish Shah, Gideon Levinsky, Jared Smolens
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Publication number: 20180024941Abstract: A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.Type: ApplicationFiled: July 20, 2016Publication date: January 25, 2018Inventors: John Pape, Manish Shah, Gideon Levinsky, Jared Smolens
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Publication number: 20170139706Abstract: An apparatus includes a buffer configured to store a plurality of instructions previously fetched from a memory, wherein each instruction of the plurality of instructions may be included in a respective thread of a plurality of threads. The apparatus also includes control circuitry configured to select a given thread of the plurality of threads dependent upon a number of instructions in the buffer that are included in the given thread. The control circuitry is also configured to fetch a respective instruction corresponding to the given thread from the memory, and to store the respective instruction in the buffer.Type: ApplicationFiled: November 18, 2015Publication date: May 18, 2017Inventors: Yuan Chou, Gideon Levinsky, Manish Shah, Robert Golla, Matthew Smittle
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Publication number: 20160055001Abstract: A method for operating an instruction buffer is disclosed. A read pointer that includes a value indicative of a given bank of a plurality of banks is received. A subset of the of the plurality of banks may then be selected dependent upon the read pointer and one or more control bits associated with an instruction stored at a location specified by the read pointer. The subset of the plurality of banks may then be activated, and an instruction read from each activated bank to form a dispatch group.Type: ApplicationFiled: August 19, 2014Publication date: February 25, 2016Inventors: Gideon Levinsky, Jama Barreh, Jia Feng
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Patent number: 9208261Abstract: An apparatus and method for saving power during TLB searches is disclosed. In one embodiment, a TLB includes a CAM having a plurality of entries each storing a virtual address, and enable logic coupled to the CAM. Responsive to initiation of a TLB query by a thread executing on a processor that includes the TLB, the enable logic is configured to enable only those CAM entries that are associated with the initiating thread. Entries in the CAM not associated with the thread are not enabled. Accordingly, an initial search of the TLB for responsive to the query is conducted only in the CAM entries that are associated with the thread. Those CAM entries that are not associated with the thread are not searched. As a result, dynamic power consumption during TLB searches may be reduced.Type: GrantFiled: January 24, 2014Date of Patent: December 8, 2015Assignee: Oracle International CorporationInventors: Manish Shah, Gideon Levinsky
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Publication number: 20150213153Abstract: An apparatus and method for saving power during TLB searches is disclosed. In one embodiment, a TLB includes a CAM having a plurality of entries each storing a virtual address, and enable logic coupled to the CAM. Responsive to initiation of a TLB query by a thread executing on a processor that includes the TLB, the enable logic is configured to enable only those CAM entries that are associated with the initiating thread. Entries in the CAM not associated with the thread are not enabled. Accordingly, an initial search of the TLB for responsive to the query is conducted only in the CAM entries that are associated with the thread. Those CAM entries that are not associated with the thread are not searched. As a result, dynamic power consumption during TLB searches may be reduced.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Inventors: Manish Shah, Gideon Levinsky
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Publication number: 20090265532Abstract: Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Applicant: SUN MICROSYSTEMS, INC.Inventors: Paul Caprioli, Sherman H. Yip, Gideon Levinsky