Abstract: A system includes a first cross-point switch receiving a first plurality of clock inputs and outputting a first plurality of clock outputs, a first plurality of buffering devices receiving the first plurality of clock outputs and outputting a first plurality of buffered clock signals synchronized with each other, a first plurality of connectors receiving the first plurality of buffered clock signals and outputting a plurality of blade signals to a plurality of blades. Each blade includes a plurality of programmable logic devices, an operation of which is synchronized based on the first plurality of clock inputs. Each blade includes a second cross-point switch to receive a blade signal of the plurality of blade signals. The second cross-point switch outputs a second plurality of clock outputs based on the received blade signal, and the second plurality of clock outputs are provided to the programmable logic devices.

Abstract: A mid-plane board including a first connector configured to receive a first signal from a first circuit board is provided. The mid-plane board includes a second connector configured to provide the first signal to a second circuit board. The first circuit board forms a first plane and the second circuit board forms a second plane, and the first plane and the second plane are substantially parallel. The mid-plane board also includes a cutout configured to allow a coplanar connector to bridge the mid-plane board and provide a second signal from the first circuit board to the second circuit board. The second signal is a high-end signal and the first signal is a low-end signal, and the mid-plane board is disposed on a plane substantially orthogonal to the first circuit board and the second circuit board.