Patents by Inventor Gijsbertus DE LANGE
Gijsbertus DE LANGE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074330Abstract: Topological superconductor devices with gates formed in two gate layers are described. A topological superconductor device includes a superconducting wire having a first junction near a first end of the superconducting wire and a second junction near a second end, opposite to the first end. The topological superconductor device further includes: (1) a first side-plunger gate and a second-side plunger gate formed in a first gate layer of the topological superconductor device, (2) a middle-plunger gate formed in the first gate layer of the topological superconductor device, (3) a first cutter gate formed in a second layer, different from the first layer, of the topological superconductor device, and (4) a second cutter gate formed in the second layer of the topological superconductor device. The plunger gates are operable to tune respective sections of the superconducting wire and the cutter gates are operable to open and close the respective junctions.Type: ApplicationFiled: November 4, 2022Publication date: February 29, 2024Inventors: Georg Wolfgang WINKLER, Farhad KARIMI, Kevin Alexander VAN HOOGDALEM, Gijsbertus DE LANGE, Jonne Verneri KOSKI, Roman Mykolayovych LUTCHYN
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Patent number: 11808796Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.Type: GrantFiled: February 15, 2022Date of Patent: November 7, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Dmitry Pikulin, Mason L Thomas, Chetan Vasudeo Nayak, Roman Mykolayovych Lutchyn, Bas Nijholt, Bernard Van Heck, Esteban Adrian Martinez, Georg Wolfgang Winkler, Gijsbertus De Lange, John David Watson, Sebastian Heedt, Torsten Karzig
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Publication number: 20230270019Abstract: A system comprises a substrate having a planar surface; a first magnet configured to apply a first magnetic field parallel to the planar surface; a circuit arranged on the planar surface; and a superconducting quantum interference device, SQUID, operably linked to the circuit. The SQUID comprises a Josephson junction arranged in a superconductive loop. The superconductive loop includes a portion which extends perpendicular to the planar surface and is orientated such that the SQUID is tuneable by the first magnet. By allowing the SQUID to be tuned using a magnetic field which is parallel to the planar surface, a reduction in flux noise may be achieved. Also provided are a method of operating a SQUID, and a SQUID.Type: ApplicationFiled: September 18, 2020Publication date: August 24, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Gijsbertus DE LANGE, Jaap Joachim WESDORP
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Publication number: 20220407482Abstract: A parametric amplifier for amplifying an input signal includes a resonator comprising a Josephson junction. The Josephson junction comprises a first superconductor component, a second superconductor component and a semiconductor component. The semiconductor component is configured to enable coupling of the first and second superconductor components. The parametric amplifier further comprises a gate electrode configured to apply an electrostatic field to the semiconductor component of the Josephson junction for tuning the parametric amplifier. Such parametric amplifiers are useful for amplifying signals in the microwave frequency range. Tuning the junction by electrostatic gating may allow for improved scalability compared to tuning using magnetic flux. Also provided are the use of the parametric amplifier to amplify a signal; and a method of amplifying a signal.Type: ApplicationFiled: November 15, 2019Publication date: December 22, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Gijsbertus DE LANGE, Wolfgang PFAFF
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Publication number: 20220299551Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.Type: ApplicationFiled: February 15, 2022Publication date: September 22, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Dmitry PIKULIN, Mason L THOMAS, Chetan Vasudeo NAYAK, Roman Mykolayovych LUTCHYN, Bas NIJHOLT, Bernard VAN HECK, Esteban Adrian MARTINEZ, Georg Wolfgang WINKLER, Gijsbertus DE LANGE, John David WATSON, Sebastian HEEDT, Torsten KARZIG
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Patent number: 11151470Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.Type: GrantFiled: May 28, 2020Date of Patent: October 19, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Dmitry Pikulin, Mason L Thomas, Chetan Vasudeo Nayak, Roman Mykolayovych Lutchyn, Georg Wolfgang Winkler, Sebastian Heedt, Gijsbertus De Lange, Bernard Van Heck, Esteban Adrian Martinez, Lucas Casparis, Torsten Karzig
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Publication number: 20210279626Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.Type: ApplicationFiled: May 28, 2020Publication date: September 9, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Dmitry PIKULIN, Mason L THOMAS, Chetan Vasudeo NAYAK, Roman Mykolayovych LUTCHYN, Georg Wolfgang WINKLER, Sebastian HEEDT, Gijsbertus DE LANGE, Bernard VAN HECK, Esteban Adrian MARTINEZ, Lucas CASPARIS, Torsten KARZIG