Abstract: Apparatuses, systems, methods, and techniques to perform graphics processing unit (GPU) initiated networking (GIN). In at least one embodiment, generation of a work queue element (WQE) is offloaded from the GPU to separate hardware (e.g., an accelerator or processor in a network interface controller). In at least one embodiment, the GPU generates a GPU-friendly descriptor (GFD), instead of a WQE, that contains information to create a WQE and transfers the GFD to the separate hardware, which performs the creation of the WQE, processes a completion queue entry (CQE), and provides a notification to the GPU that processing the WQE has been completed.

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

Abstract: A network device for load balancing in a multiplane network comprises a software stack that formats a data flow for transmission, and one or more circuits that identify the formatted data flow as a fixed data flow, and apply software-based load balancing to select a first plane, from among a plurality of planes of the multiplane network, for transmitting one or more data packets of the fixed data flow.

Abstract: A system includes one or more processors, one or more network devices, and a controller device. The network devices are to exchange communication traffic over a network for the one or more processors, by executing work requests issued by the one or more processors. The controller device is to receive the work requests from the one or more processors and distribute the work requests among the network devices.

Abstract: Systems and methods herein are for multicast configurations in a network using a switch that can receive communication for a multicast group and that can transmit at least data from the communication to different destination nodes. The communication may include, in addition to the data, a multicast identifier associated with first egress ports of the switch and a bitmask representation associated with second egress ports of the switch. The transmission of the data can occur through the first egress ports and the second egress ports to reach the different destination nodes.

Abstract: In one embodiment, a network switch device includes a network interface to receive vectors from endpoint devices, and an aggregation and reduction accelerator to perform elementwise and vector splitting operations with the vectors as input yielding at least two intermediate vector results, wherein the network interface is to send the at least two intermediate vector results to different corresponding network switches in different switch aggregation trees, receive at least two final vector results of an aggregation and reduction process from the different switch aggregation trees, and combine the at least two final vector results to yield a combined final vector result, wherein the network interface is to send the combined final vector result to the endpoint devices.

Abstract: A system includes one or more processors, and multiple network devices to connect the one or more processors to a network. The one or more processors are to issue work requests to the multiple network devices, by posting work descriptors on one or more shared queues that are each accessible to the multiple network devices. The network devices are to pull the work descriptors from the one or more shared queues, and to execute the work requests responsively to the work descriptors.

Abstract: A system includes at least one processing node to perform one or more compute processes as part of a distributed workload to generate an output. The at least one processing node is configured with a derived seed value that is generated from a base seed value. The system further includes a rounding circuit to perform rounding operations for the at least one processing node according to the derived seed value.

Abstract: In one embodiment, a parallel computing system includes a key manager to assign symmetric memory keys to parallel computing jobs including a first symmetric memory key to a first parallel computing job, and a plurality of server nodes to execute parallel computing processes of the first parallel computing job, and cause registration of host memory regions of the server nodes with the assigned first symmetric memory key in corresponding network interface controllers of the server nodes so that different ones of the host memory regions are accessible with the first symmetric memory key by remote ones of the server nodes using remote direct memory access.

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry, and retrieve WRs from the multiple NSQs and execute data transmission operations specified in the WRs retrieved from the multiple NSQs.

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

Abstract: In one embodiment, a network switch device includes a network interface to receive vectors from endpoint devices, and an aggregation and reduction accelerator to perform elementwise and vector splitting operations with the vectors as input yielding at least two intermediate vector results, wherein the network interface is to send the at least two intermediate vector results to different corresponding network switches in different switch aggregation trees, receive at least two final vector results of an aggregation and reduction process from the different switch aggregation trees, and combine the at least two final vector results to yield a combined final vector result, wherein the network interface is to send the combined final vector result to the endpoint devices.

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

Abstract: A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.

Abstract: A method includes providing a plurality of processes interconnected by a network, each of the plurality of processes being configured to hold a block of data destined for others of the plurality of processes. A set of data for all-to-all data exchange is received from one or more of the processes. The set of data is configured as a plurality of blocks of data in a matrix as matrix data, the matrix being distributed among the plurality of processes. The matrix data is transposed by changing the position of selected blocks of data of the plurality of blocks of data relative to the other blocks of data of the plurality of the blocks of data, without changing the structure of each of the blocks of data. The transposed matrix data is over the network and is then received, repacked, and conveyed to destination processes.

Abstract: Systems and methods herein are for message or data aggregation in computer networks in which at least one processor of a network module receives communication including messages having data, determines destination host machines for the messages, and aggregates a subset of the messages or the data to be transmitted to one of different destination host machines, where the aggregation is based at least in part on a bandwidth and a buffer availability associated with the one destination host machine, and where the buffer availability is determined from a status communication between the one destination host machine and the host machine.

Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.