Patents by Inventor Gil Drori

Gil Drori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for accessing a multi ordered memory array
    Patent number: 8166275
    Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 24, 2012
    Assignee: Ceva D.S.P. Ltd.
    Inventors: Gil Drori, Omri Eisenbach, Erez Bar Niv, David Dahan
  • System and method for providing mutual breakpoint capabilities in computing device
    Patent number: 7523351
    Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 21, 2009
    Assignee: Ceva D.S.P. Ltd
    Inventors: Gil Drori, Erez Bar-Niv, David Dahan, Omri Eisenbach
  • System and method for providing mutual breakpoint capabilities in a computing device
    Patent number: 7467332
    Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: December 16, 2008
    Assignee: Ceva D.S.P. Ltd
    Inventors: Gil Drori, Erez Bar-Niv, David Dahan, Omir Eisenbach
  • METHOD AND APPARATUS FOR ACCESSING A MULTI ORDERED MEMORY ARRAY
    Publication number: 20080052460
    Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 28, 2008
    Applicant: CEVA D.S.P. LTD.
    Inventors: Gil DRORI, Erez Bar Niv, David Dahan
  • System and method for providing mutual breakpoint capabilities in a computing device
    Publication number: 20060085684
    Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.
    Type: Application
    Filed: February 14, 2005
    Publication date: April 20, 2006
    Applicant: CEVA D.S.P. LTD.
    Inventors: Gil Drori, Erez Bar-Niv, David Dahan, Omri Eisenbach
  • System and method for providing mutual breakpoint capabilities in computing device
    Publication number: 20060075298
    Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.
    Type: Application
    Filed: November 12, 2004
    Publication date: April 6, 2006
    Applicant: CEVA D.S.P. LTD.
    Inventors: Gil Drori, Erez Bar-Niv, David Dahan, Omir Eisenbach
  • Method and apparatus for accessing a multi ordered memory array
    Publication number: 20050262275
    Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.
    Type: Application
    Filed: May 19, 2004
    Publication date: November 24, 2005
    Inventors: Gil Drori, Erez Niv, David Dahan