Abstract: A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer

Abstract: Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When farming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: An oxide layer is selectively formed on a layer including silicon by a plasma process using hydrogen gas and a gas including oxygen. The hydrogen gas is controlled to have a flow rate less than about 50 percent of an overall flow rate by adding helium gas to the plasma process.

Abstract: A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

Abstract: Semiconductor devices and methods of fabricating the same are provided. A gate insulating film is provided on a semiconductor substrate. A polymetal gate electrode is provided on the gate insulating film. The polymetal gate electrode includes a conductive polysilicon film on the gate insulating film, a first metal silicide film on the conductive polysilicon film, a barrier film on the first metal silicide film, and a metal film on the barrier film. The barrier film includes a titanium nitride (TiN) film on the first metal silicide film and a buffer layer between the TiN film and the metal film.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.

Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.

Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.

Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

Abstract: A bonding pad structure for a semiconductor device includes a first lower metal layer beneath a second upper metal layer in a bonding region of the device. The lower metal layer is formed such that the metal of the lower metal layer is absent from the bonding region. As a result, if damage occurs to the structure during procedures such as probing or bonding at the bonding region, the lower metal is not exposed to the environment. Oxidation of the lower metal layer by exposure to the environment is prevented, thus improving reliability of the device.

Abstract: A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern.

Abstract: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.

Abstract: A method of fabricating an integrated circuit capacitor includes forming a first metal layer on a conductive plug in an interlayer insulating layer on a substrate. At least a portion of the first metal layer is silicided to form a metal silicide layer and a remaining first metal layer on the conductive plug. The remaining first metal layer is removed using a dry etching process. A lower electrode including a second metal layer is then formed on the metal silicide layer. Because the remaining first metal layer is removed, etching and/or other damage to the conductive plug and/or the interlayer insulating layer during a subsequent wet ethching process may be reduced and/or prevented.

Abstract: A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second processing chamber. The transfer chamber is configured to transfer the semiconductor substrate between the first processing chamber and the second processing chamber.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: A metal layer can be formed in an integrated circuit by forming a metal-nitride layer in a recess including a first concentration of nitrogen in the metal-nitride layer at a bottom of the recess that is less than a second concentration of nitrogen in the metal-nitride layer proximate an opening of the recess. A metal layer can be formed on the metal-nitride layer including in the recess.