Patents by Inventor GIL HOROVITZ
GIL HOROVITZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824576Abstract: An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.Type: GrantFiled: September 24, 2020Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Ofir Degani, Gil Horovitz, Evgeny Shumaker, Sergey Bershansky, Aryeh Farber, Igor Gertman, Run Levinger
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Patent number: 11558059Abstract: Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station.Type: GrantFiled: August 27, 2020Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Igal Kushnir, Evgeny Shumaker, Aryeh Farber, Gil Horovitz
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Publication number: 20220278690Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.Type: ApplicationFiled: June 23, 2021Publication date: September 1, 2022Inventors: Evgeny SHUMAKER, Elan BANIN, Ofir DEGANI, Gil HOROVITZ
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Publication number: 20220094385Abstract: An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.Type: ApplicationFiled: September 24, 2020Publication date: March 24, 2022Inventors: Ofir DEGANI, Gil HOROVITZ, Evgeny SHUMAKER, Sergey BERSHANSKY, Aryeh FARBER, Igor GERTMAN, Run LEVINGER
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Patent number: 11283426Abstract: An electrical device (100) that comprises at least one signal filter (104) comprising a plurality of mechanical resonators (106 108, 110) in a substrate (102) and at least one further mechanical resonator (112) in the substrate (102) configured to oscillate at a reference frequency of an oscillator signal. An electrical system (300) comprising an electrical oscillator (306) a transceiver (302) and an antenna (310), and an electrical device (100). A method (1300) for providing an electrical device (100).Type: GrantFiled: December 29, 2017Date of Patent: March 22, 2022Assignee: Apple Inc.Inventors: Igal Kushnir, Harry Skinner, Bernhard Raaf, Sharon Malevsky, Gil Horovitz
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Patent number: 11264997Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.Type: GrantFiled: October 9, 2020Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
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Patent number: 11237195Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.Type: GrantFiled: June 26, 2017Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Sarit Zur, Igal Kushnir, Gil Horovitz, Rotem Banin, Sergey Bershansky
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Publication number: 20210203333Abstract: Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station. The digitally controlled oscillator circuit arrangement comprises input circuitry for obtaining a frequency setting signal, the frequency setting signal comprising a plurality of signal components, selection circuitry for selecting one signal component of the plurality of signal components of the frequency setting signal based on an oscillation signal of the digitally controlled oscillator circuit arrangement, signal generation circuitry for generating the oscillation signal based on the selected signal component of the frequency setting signal, and output circuitry for providing the oscillation signal.Type: ApplicationFiled: August 27, 2020Publication date: July 1, 2021Inventors: Igal KUSHNIR, Evgeny SHUMAKER, Aryeh FARBER, Gil HOROVITZ
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Patent number: 11005481Abstract: A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency.Type: GrantFiled: November 29, 2018Date of Patent: May 11, 2021Assignee: Apple Inc.Inventors: Evgeny Shumaker, Gil Horovitz
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Publication number: 20210116871Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.Type: ApplicationFiled: June 26, 2017Publication date: April 22, 2021Inventors: Sarit Zur, Igal Kushnir, Gil Horovitz, Rotem Banin, Sergey Bershansky
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Patent number: 10938396Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.Type: GrantFiled: March 13, 2019Date of Patent: March 2, 2021Assignee: Apple Inc.Inventors: Abhishek Agrawal, Alon Cohen, Gil Horovitz, Somnath Kundu, Run Levinger, Stefano Pellerano, Jahnavi Sharma, Evgeny Shumaker, Izhak Hod
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Publication number: 20210050857Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.Type: ApplicationFiled: October 9, 2020Publication date: February 18, 2021Inventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
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Publication number: 20200395916Abstract: An electrical device (100) that comprises at least one signal filter (104) comprising a plurality of mechanical resonators (106 108, 110) in a substrate (102) and at least one further mechanical resonator (112) in the substrate (102) configured to oscillate at a reference frequency of an oscillator signal. An electrical system (300) comprising an electrical oscillator (306) a transceiver (302) and an antenna (310), and an electrical device (100). A method (1300) for providing an electrical device (100).Type: ApplicationFiled: December 29, 2017Publication date: December 17, 2020Inventors: Igal Kushnir, Harry Skinner, Bernhard Raaf, Sharon Malevsky, Gil Horovitz
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Patent number: 10809669Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.Type: GrantFiled: October 14, 2019Date of Patent: October 20, 2020Assignee: Intel CorporationInventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir
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Patent number: 10804911Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.Type: GrantFiled: March 5, 2019Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
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Publication number: 20200295765Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.Type: ApplicationFiled: March 13, 2019Publication date: September 17, 2020Inventors: Abhishek Agrawal, Alon Cohen, Gil Horovitz, Somnath Kundu, Run Levinger, Stefano Pellerano, Jahnavi Sharma, Evgeny Shumaker, Izhak Hod
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Publication number: 20200287557Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.Type: ApplicationFiled: March 5, 2019Publication date: September 10, 2020Inventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
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Patent number: 10768580Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.Type: GrantFiled: March 2, 2017Date of Patent: September 8, 2020Assignee: Intel IP CorporationInventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
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Patent number: 10707880Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.Type: GrantFiled: January 24, 2017Date of Patent: July 7, 2020Assignee: Intel IP CorporationInventors: Elan Banin, Tamar Marom, Gil Horovitz, Rotem Banin
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Publication number: 20200201263Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.Type: ApplicationFiled: October 14, 2019Publication date: June 25, 2020Inventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir