Abstract: A method for traffic control in a network on chip that includes a group of routers and a group of processing engines (PEs). The method includes (i) obtaining, by a source PE that is coupled to a sub-group of routers via a sub-group of channels, backpressure information related to sub-group of channels; (ii) selecting, by the source PE, a selected channel of the sub-group of channels for conveying a packet destined to reach a destination PE; wherein the selecting is based, at least in part, on the backpressure information; wherein the source PE and the destination PE belong to the group of PEs; wherein the sub-group of routers belong to the group of routers; and (iii) outputting the packet to the selected channel.

Abstract: There may be provided a method for traffic control in a network on chip (NOC), the method may include receiving, by input interface units of the NOC, flow control units destined to output interface units of the NOC; wherein multiple routing paths span between the input interface units and the output interface units; wherein at least some of the routing paths are formed by multiple routers of a grid of routers of the NOC and have a single turning point; allocating virtual channels to the flow control units, wherein an allocating of a virtual channel to a flow control unit (FCU) is based on a type of a transaction associated with the FCU and on a location of the single turning point; and routing the flow control units, based on the virtual channels allocated to the FCUs, between the input interface units and the output interface units.

Abstract: A data plane integrated circuit that includes interfacing units (IFUs), Datapath units (DPUs); and a network on chip (NoC). The DPUs are arranged in local sets of DPUs that are proximate to each other, each local set is configured to (a) store an instance of packet header processing control data structures and (b) independently perform local packet header processing and transmission scheduling.

Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected profile from plural profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected profile for a selected least recently used (LRU) position in the cache.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.

Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected access profile from plural access profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected access profile for a selected least recently used (LRU) position in the cache.

Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event.

Abstract: A token bucket management apparatus comprises a processing resource having an input for receiving profile data associated with a classified data stream. The processing resource also comprises an arithmetic unit arranged to maintain a bucket status value for a token bucket associated with the classified data stream. The arithmetic unit is a fixed point arithmetic unit that is arranged to maintain the bucket status value in accordance with a fixed point representation of non-integer numbers having a first accuracy. The arithmetic unit calculates a fixed point non-integer increment value in accordance with a fixed point representation of non-integer numbers having a second accuracy. The arithmetic unit is arranged to manipulate the calculated non-integer increment value so as to bring the second accuracy into agreement with the first accuracy, and to increment the bucket status value by the manipulated non-integer increment value.

Abstract: A counters array system comprises a memory device having a plurality of addressable memory locations for storing counter-values; a plurality of delta-counter devices. Each delta-counter device is operable to hold a maximum delta-value corresponding to a maximum number of occurrences of an event during a time duration between two counter scans controlled by a scan control unit. Each delta-counter device has an input connected to receive a signal from an event source corresponding to an occurrence of the event, and an output connected to provide a delta-value representing an accumulated number of occurrences of the event to a delta-count update circuit. The delta-count update circuit is connected to the memory device and the counter scan control unit, and being arranged to receive the delta-value and an address of a corresponding counter-value, read the counter-value from the memory device, and provide an updated counter-value incremented by the delta-value to the memory device.

Abstract: A token bucket management apparatus comprises a processing resource having an input for receiving profile data associated with a classified data stream. The processing resource also comprises an arithmetic unit arranged to maintain a bucket status value for a token bucket associated with the classified data stream. The arithmetic unit is a fixed point arithmetic unit that is arranged to maintain the bucket status value in accordance with a fixed point representation of non-integer numbers having a first accuracy. The arithmetic unit calculates a fixed point non-integer increment value in accordance with a fixed point representation of non-integer numbers having a second accuracy. The arithmetic unit is arranged to manipulate the calculated non-integer increment value so as to bring the second accuracy into agreement with the first accuracy, and to increment the bucket status value by the manipulated non-integer increment value.

Abstract: A counters array system comprises a memory device having a plurality of addressable memory locations for storing counter-values; a plurality of delta-counter devices. Each delta-counter device is operable to hold a maximum delta-value corresponding to a maximum number of occurrences of an event during a time duration between two counter scans controlled by a scan control unit. Each delta-counter device has an input connected to receive a signal from an event source corresponding to an occurrence of the event, and an output connected to provide a delta-value representing an accumulated number of occurrences of the event to a delta-count update circuit. The delta-count update circuit is connected to the memory device and the counter scan control unit, and being arranged to receive the delta-value and an address of a corresponding counter-value, read the counter-value from the memory device, and provide an updated counter-value incremented by the delta-value to the memory device.

Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event.

Abstract: A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests.

Abstract: A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests.