Patents by Inventor Gil Naveh

Gil Naveh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9058209
    Abstract: An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a second value at least in part by multiplying each of a portion of the samples by respective ones of a second set of values for the impulse response and summing the results. The data processing system is operative to determine the power of the tone in the multiple samples of the input signal at least in part by utilizing the first value and the second value.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: June 16, 2015
    Assignee: Intel Corporation
    Inventor: Gil Naveh
  • Publication number: 20130268571
    Abstract: An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a second value at least in part by multiplying each of a portion of the samples by respective ones of a second set of values for the impulse response and summing the results. The data processing system is operative to determine the power of the tone in the multiple samples of the input signal at least in part by utilizing the first value and the second value.
    Type: Application
    Filed: April 9, 2012
    Publication date: October 10, 2013
    Applicant: LSI CORPORATION
    Inventor: Gil Naveh
  • Patent number: 8503584
    Abstract: A method of detecting received data in a communication system includes the steps of: performing a QR decomposition on a received input vector as a function of one or more characteristics of a communication channel over which the input vector was transmitted; generating a subset of best symbol candidates from a symbol constellation by comparing an input sample (corresponding to an element of the input vector) with one or more prescribed thresholds; identifying at least one symbol satisfying prescribed minimum Euclidian distance criteria among multiple ambiguity symbols in the subset of best symbol candidates; and generating a subset of best symbols including a prescribed number of symbols from the symbol constellation determined to be closest to the input sample. The subset of best symbols is used in a subsequent iteration of the steps of generating the subset of best symbol candidates and identifying at least one symbol satisfying the prescribed minimum Euclidian distance criteria.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 6, 2013
    Assignee: LSI Corporation
    Inventors: Gennady Zilberman, Eliahou Arviv, Daniel Briker, Gil Naveh, Moshe Bukris
  • Publication number: 20120155579
    Abstract: A method of detecting received data in a communication system includes the steps of: performing a QR decomposition on a received input vector as a function of one or more characteristics of a communication channel over which the input vector was transmitted; generating a subset of best symbol candidates from a symbol constellation by comparing an input sample (corresponding to an element of the input vector) with one or more prescribed thresholds; identifying at least one symbol satisfying prescribed minimum Euclidian distance criteria among multiple ambiguity symbols in the subset of best symbol candidates; and generating a subset of best symbols including a prescribed number of symbols from the symbol constellation determined to be closest to the input sample. The subset of best symbols is used in a subsequent iteration of the steps of generating the subset of best symbol candidates and identifying at least one symbol satisfying the prescribed minimum Euclidian distance criteria.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Inventors: Gennady Zilberman, Eliahou Arviv, Daniel Briker, Gil Naveh, Moshe Bukris
  • Publication number: 20050071830
    Abstract: An information handling system processes a sequence of instructions that includes first and second instructions. Each of the first and second instructions is processable in a sequence of stages that includes first and second execution stages. The first instruction's second execution stage is processable substantially concurrent with processing the second instruction's first execution stage. The first instruction is executed during its second execution stage. The second instruction is executed during a selected one of its first and second execution stages. A computer program product includes apparatus from which a computer program is accessible by an information handling system. The computer program is processable by the information handling system for causing the information handling system to assemble the sequence of instructions.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Applicant: StarCore, LLC
    Inventor: Gil Naveh
  • Patent number: 6411978
    Abstract: A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by two invoked by comparison with a fixed comparison constant. Unfortunately, the fixed comparison constant is not always optimum for maximizing the signal to quantization noise ratio, which is degraded by excessive scale down. Moreover, current mechanisms are limited to the radix-2 block floating point FFT. The processor of the present invention provides the programmer with a FFT compare register which is loadable under program control, thus allowing the programmer to adjust the threshold at which scale down of the stage output is activated for better control over the signal to quantization noise ratio. In addition, the present invention supports other FFT structures besides the radix-2 block floating point FFT.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: June 25, 2002
    Assignee: Infineon Technologies Ag I. Gr.
    Inventors: Gil Naveh, Eran Weingarten, Haim Granot