Abstract: The present invention includes compositions, devices and methods for filling structures of high aspect ratio elements for growth amplification and device fabrication. A method includes a method of filling a structure comprising the steps of providing one or more structures, each structure having a plurality of high aspect ratio elements, wherein the aspect ratio is at least 5; and coating the plurality of high aspect ratio elements with at least one solidifying material produced by a form of chemical vapor deposition thereby forming a structured-film. Compositions of the present invention are solid formed structures that are less fragile, do not require such delicate handling to avoid serious degradation, are more stable, last longer, do not deform, and exhibit little stress as well as improved properties that include mechanical, chemical, electrical, biologic, and optical.

Abstract: High-quality SiO.sub.2 films may be deposited at low temperatures by plasma-enhanced chemical vapor deposition using disilane (Si.sub.2 H.sub.6) and nitrous oxide (N.sub.2 O) as silicon and oxygen precursors in an otherwise conventional reactor such as a parallel plate plasma reactor. The properties of the SiO.sub.2 films deposited at 120.degree. C. using Si.sub.2 H.sub.6 and N.sub.2 O were not significantly different from those of conventional SiH.sub.4 -based SiO.sub.2 films deposited at the significantly higher temperature range 250.degree.-350.degree. C. PECVD deposition of SiO.sub.2 films using Si.sub.2 H.sub.6 and N.sub.2 O provides a practical low temperature process for fabricating microdevices and circuits. This low temperature process can be used for deposition in the presence of polymers, semiconductors, and other components that would melt, decompose, or otherwise be sensitive to higher temperatures. Fluorinated silicon oxide may also be deposited at the relatively low temperature of 120.degree.

Abstract: An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudo-random test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.

Abstract: A clock driver circuit for low level gates having high fanout capabilities includes a first circuit portion, a second circuit portion, an output transistor and a load resistor. The first circuit portion is formed of a first NAND logic gate and a first inverter gate. The input node of the first inverter circuit gate is coupled to the output node of the first NAND gate. The input node of the first NAND gate is connected to an input circuit terminal. The second circuit portion is formed of a second NAND logic gate, a third NAND logic gate and a second inverter gate. The input nodes of the second and third NAND gates are coupled together and to the input circuit terminal. The output node of the second and third NAND gates are coupled together and to the input node of the second inverter gate. The output node of the second inverter gate is connected to an output circuit terminal.

Abstract: A line receiver circuit having an input hysteresis characteristic which is compensated for both temperature changes and variations in supply voltage includes a receiver circuit portion, a bandgap circuit portion, a first voltage divider network, a second voltage divider network, and a feedback switching transistor. The receiver circuit portion is responsive to an input logic signal for generating an output signal. The bandgap circuit portion generates a constant reference voltage. The first and second voltage divider networks are operatively connected to the constant reference voltage. The switching transistor is responsive to the output signal for switching between the first voltage divider network generating a high threshold voltage when the input logic signal is in the low level state and the second voltage divider network generating a low threshold voltage when the input logic signal is in the high level state.

Abstract: A non-inverting high speed low level gate to Schottky transistor logic translator circuit includes a first input circuit adapted for receiving a first input signal and having its outputs connected to a first node and a second node. A first Schottky transistor is provided which has its base connected to the first node and to a voltage supply potential via a first resistor, its emitter connected to the second node and its collector connected to a third node and to the supply potential via a second resistor. A second Schottky transistor is provided which has its base coupled to the third node, its collector connected to the supply potential via a third resistor and its emitter connected to a fourth node. An upper output transistor has its base connected to the fourth node and to a ground potential via a fourth resistor, its collector connected to the supply potential via a fifth resistor and its emitter connected to an output circuit terminal.