Abstract: Generating photonic graph states includes positioning a plurality of quantum emitters at a plurality of coupling sites associated with a plurality of cavities and initializing a state of a quantum emitter qubit associated with each of the plurality of quantum emitters. Photonic qubits are transmitted toward the plurality of the quantum emitters a first instance transmission for generating an entangling gate between the photonic qubits and the quantum emitter qubit in order to entangle the quantum emitter qubit and the photonic qubits. Following the first instance transmission, photonic qubits are transmitted toward the plurality of quantum emitters in a one second instance transmission for generating a SWAP gate between the photonic qubits and the quantum emitter qubits to map the quantum emitter qubits to photonic qubits.

Abstract: A quantum computing system includes a first resonator couplable to a first alkali atom, a second resonator couplable to a second alkali atom, and lasers for trapping, cooling, and manipulating the first alkali atom and the second alkali atom. Detectors detect a presence of the trapped first alkali atom and the trapped second alkali atom, and a processor is configured to receive at least one input signal from at least one of the detectors, the input signal indicating a presence of the trapped first alkali atom and the trapped second alkali atom, and, based on the received input, control at least some of the lasers to manipulate at least one of the trapped first alkali atom and the trapped second alkali atom to thereby generate photonic qubits using the trapped first alkali atom or generate entanglement between photonic qubits transmitted to the trapped second alkali atom.

Abstract: A quantum computing system, method and computer readable storage medium involve tuning a whispering-gallery mode optical resonator to support a resonance frequency associated with a transition frequency of an atom. Operation of a laser is controlled to cause the atom to be trapped adjacent the optical resonator and within the evanescent field portion. Based on an atom presence signal from an optical atom presence detector, an indication is provided that the atom is trapped adjacent the optical resonator. A frequency of a cooling laser is controlled to cool the atom, and the optical resonator is configured to define a closed loop-like mode including an evanescent field portion. The trapping laser is configured to cause the atom to be trapped adjacent the whispering-gallery mode resonator, and the cooling laser is configured to manipulate a state of the atom to thereby cool the atom.

Abstract: A quantum computing system comprises a plurality of photonic cavities, a plurality of coupling locations for quantum emitter positioning, a photon generator configured to supply photons to the plurality of photonic cavities, and a plurality of photon output channels downstream of the plurality of cavities to output a graph state. Each coupling location is associated with a differing one of the plurality of photonic cavities. Quantum emitters associated with each coupling location are configured to mediate interactions between consecutive incoming photonic qubits to generate the graph state, and the photonic cavities are configured to couple photonic qubits to the quantum emitters.

Abstract: A quantum computing system includes a first silicon nitride resonator couplable to a first alkali atom, a second silicon resonator couplable to a second alkali atom, and a plurality of lasers for trapping, cooling, and manipulating the first alkali atom and the second alkali atom. Detectors detect a presence of the trapped first alkali atom and the trapped second alkali atom, and a processor is configured to receive at least one input signal from at least one of the detectors, the input signal indicating a presence of the trapped first alkali atom and the trapped second alkali atom, and, based on the received input, control at least some of the plurality of lasers to manipulate at least one of the trapped first alkali atom and the trapped second alkali atom to thereby generate photonic qubits using the trapped first alkali atom or generate entanglement between photonic qubits transmitted to the trapped second alkali atom.

Abstract: A quantum computing system includes a first silicon nitride resonator couplable to a first alkali atom, a second silicon resonator couplable to a second alkali atom, and a plurality of lasers for trapping, cooling, and manipulating the first alkali atom and the second alkali atom. Detectors detect a presence of the trapped first alkali atom and the trapped second alkali atom, and a processor is configured to receive at least one input signal from at least one of the detectors, the input signal indicating a presence of the trapped first alkali atom and the trapped second alkali atom, and, based on the received input, control at least some of the plurality of lasers to manipulate at least one of the trapped first alkali atom and the trapped second alkali atom to thereby generate photonic qubits using the trapped first alkali atom or generate entanglement between photonic qubits transmitted to the trapped second alkali atom.

Abstract: Generating photonic graph states includes positioning a plurality of quantum emitters at a plurality of coupling sites associated with a plurality of cavities and initializing a state of a quantum emitter qubit associated with each of the plurality of quantum emitters. Photonic qubits are transmitted toward the plurality of the quantum emitters a first instance transmission for generating an entangling gate between the photonic qubits and the quantum emitter qubit in order to entangle the quantum emitter qubit and the photonic qubits. Following the first instance transmission, photonic qubits are transmitted toward the plurality of quantum emitters in a one second instance transmission for generating a SWAP gate between the photonic qubits and the quantum emitter qubits to map the quantum emitter qubits to photonic qubits.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: An apparatus for use with a memory device that has a plurality of memory-device terminals having respective unique bit significances is described. The apparatus includes a memory controller, which includes (i) a plurality of external terminals, each one of the external terminals configured to be in communication with a respective one of the memory-device terminals, (ii) a plurality of internal terminals having respective unique bit significances, (iii) a switching unit, and (iv) a processor. The processor is configured to drive the memory device to communicate a predetermined sequence of bit patterns to the controller, and, in response to the sequence of bit patterns, drive the switching unit to connect each one of the external terminals to a respective one of the internal terminals having the bit significance of the memory-device terminal with which the external terminal is in communication. Other embodiments are also described.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: A device includes multiple memory devices, a bus splitter and a package. The bus splitter is configured to exchange storage commands and data with an external host using an external Input/Output (I/O) bus, and to distribute the storage commands and the data over multiple buses connected to respective subsets of the memory devices, so as to relay the storage commands and the data between the multiple memory devices and the external host. The memory devices and the bus splitter are contained in the package, in a multi-chip package (MCP) structure.

Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: A method for data storage in a memory that includes a plurality of analog memory cells includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.