Abstract: A method, apparatus and product for testing a system under development. The method comprises obtaining information including a current version of a code, and predicting that a subset of code elements from the current version of the code are bug-prone elements. The method comprises determining one or more coverage events corresponding to the bug-prone elements. The method further comprises determining a testing policy based on the one or more coverage events that correspond to the bug-prone elements, wherein the testing policy is determined based on a statistical analysis of coverage likelihood of tests generated based on a test template for each coverage event of the one or more coverage events. The method further comprises implementing the testing policy.

Abstract: A method, apparatus and product for testing a system under development. The method comprises obtaining information including a current version of a code, and predicting that a subset of code elements from the current version of the code are bug-prone elements. The method comprises determining one or more coverage events corresponding to the bug-prone elements. The method further comprises determining a testing policy based on the one or more coverage events that correspond to the bug-prone elements, wherein the testing policy is determined based on a statistical analysis of coverage likelihood of tests generated based on a test template for each coverage event of the one or more coverage events. The method further comprises implementing the testing policy.

Abstract: A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.

Abstract: A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.

Abstract: A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.

Abstract: A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.

Abstract: A method comprising using at least one hardware processor for: providing a plurality of behavioral models of vehicular components; providing a plurality of simulated vehicular components; providing a model of interaction between at least some of said vehicular components; and generating a simulation test for said vehicular components by defining continuous behavioral functions for said plurality of behavioral models and for said plurality of simulated vehicular components, wherein each of said continuous behavioral functions comprises a superimposition of a finite number of continuous functions each having a finite number of parameters, and wherein at least some of said continuous behavioral functions interrelate in accordance with said model of interaction.

Abstract: Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.

Abstract: Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.

Abstract: A method for solving a constraint satisfaction problem includes receiving a set of variables having respective input domains and a set of relations among the variables, and building a network of one or more hyper-arcs representative of the set of relations, each hyper-arc corresponding to one of the relations and linking nodes in the network corresponding to the variables that are subject to the relation. For each of the hyper-arcs, the variables are assembled in a hierarchy based on the relation corresponding to the hyper-arc. The input domains of the variables in the hierarchy are reduced, so as to determine respective output domains of the variables that are consistent with the relations.

Abstract: A method for solving a constraint satisfaction problem includes receiving a set of variables having respective input domains and a set of relations among the variables, and building a network of one or more hyper-arcs representative of the set of relations, each hyper-arc corresponding to one of the relations and linking nodes in the network corresponding to the variables that are subject to the relation. For each of the hyper-arcs, the variables are assembled in a hierarchy based on the relation corresponding to the hyper-arc. The input domains of the variables in the hierarchy are reduced, so as to determine respective output domains of the variables that are consistent with the relations.