Abstract: A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.

Abstract: Disclosed is a miniaturized battery module in which a space except for a space of a battery cell is minimized and the number of components is reduced. The miniaturized battery module includes a cell assembly configured by assembling a plurality of battery cells, an upper frame inserted into an outer upper surface of the cell assembly, a lower frame inserted into an outer lower surface of the cell assembly and fastened to the upper frame, and first and second endplates fastened to two opposite ends of the cell assembly and configured to fix the plurality of battery cells. In this case, at least two or more of the plurality of the battery cells are arranged side by side, and the upper frame and the lower frame are fastened by welding.

Abstract: A decoupling circuit and a semiconductor device including the same are provided. The decoupling circuit includes a first circuit including a first capacitor having a first end connected to a first terminal, a first switch device connected between a second end of the first capacitor and a second terminal, and a first control device configured to turn on/off the first switch device based on a voltage level of the a second end of the first capacitor, and a second circuit including a second capacitor having a first end connected to the first terminal, a second switch device connected between a second end of the second capacitor and the second terminal, and a second control device configured to turn on/off the second switch device based on a voltage level of the second end of the second capacitor and an output signal of the first control device.

Abstract: A decoupling circuit and a semiconductor device including the same are provided. The decoupling circuit includes a first circuit including a first capacitor having a first end connected to a first terminal, a first switch device connected between a second end of the first capacitor and a second terminal, and a first control device configured to turn on/off the first switch device based on a voltage level of the a second end of the first capacitor, and a second circuit including a second capacitor having a first end connected to the first terminal, a second switch device connected between a second end of the second capacitor and the second terminal, and a second control device configured to turn on/off the second switch device based on a voltage level of the second end of the second capacitor and an output signal of the first control device.

Abstract: A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract: A method for reading data stored in a fuse device included in a memory device including a memory cell array is provided. The method comprises reading trimming data of the fuse device, wherein the trimming data is related to trimming a level of voltage or a level of current used for an operation of the memory device; and after the reading the trimming data, reading defective cell address data of the fuse device, wherein the defective cell address data is related to defective cells in the memory cell array.

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract: An electronic relay includes: a housing having an interior space therein and a lateral side and a lower side of which are opened, a board installation part being formed along a periphery of the opened side of the housing; a printed circuit board a periphery of which is inserted into and installed in the board installation part of the housing, for shielding the opened side of the housing and performing a switching function; a lower cover for shielding a lower side of the housing, one side edge of the printed circuit board being fixed to the lower cover; and terminals ends of which are electrically connected to the printed circuit board and opposite ends of which pass through the lower cover to protrude to the outside.

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract: A method for reading data stored in a fuse device included in a memory device including a memory cell array is provided. The method comprises reading trimming data of the fuse device, wherein the trimming data is related to trimming a level of voltage or a level of current used for an operation of the memory device; and after the reading the trimming data, reading defective cell address data of the fuse device, wherein the defective cell address data is related to defective cells in the memory cell array.

Abstract: A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

Abstract: An electronic relay includes: a housing having an interior space therein and a lateral side and a lower side of which are opened, a board installation part being formed along a periphery of the opened side of the housing; a printed circuit board a periphery of which is inserted into and installed in the board installation part of the housing, for shielding the opened side of the housing and performing a switching function; a lower cover for shielding a lower side of the housing, one side edge of the printed circuit board being fixed to the lower cover; and terminals ends of which are electrically connected to the printed circuit board and opposite ends of which pass through the lower cover to protrude to the outside.

Abstract: An optical receiver with a threshold voltage convergence and audio apparatus and communication apparatus using the optical receiver are provided. The optical receiver of the present invention includes an optical detector for converting a received optical signal to a current signal; a transimpedance amplifier for converting the current signal to a voltage signal; a level shifter for converging the voltage signal to a threshold voltage by removing an offset of the voltage signal, the level shifter comprising a plurality of linear subtractors connected in series; a reference voltage generator for generating a reference voltage in proportion to a variation of the offset of the voltage signal; and a comparator for comparing the threshold voltage and the reference voltage and generating a digital signal of a logic level according to a comparison result.

Abstract: In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.

Abstract: An optical receiver with a threshold voltage convergence and audio apparatus and communication apparatus using the optical receiver are provided. The optical receiver of the present invention includes an optical detector for converting a received optical signal to a current signal; a transimpedance amplifier for converting the current signal to a voltage signal; a level shifter for converging the voltage signal to a threshold voltage by removing an offset of the voltage signal, the level shifter comprising a plurality of linear subtractors connected in series; a reference voltage generator for generating a reference voltage in proportion to a variation of the offset of the voltage signal; and a comparator for comparing the threshold voltage and the reference voltage and generating a digital signal of a logic level according to a comparison result.

Abstract: In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.