Patents by Inventor Gil-sub Kim
Gil-sub Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8759945Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.Type: GrantFiled: April 7, 2011Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim, Ho-Ju Song
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Patent number: 8697579Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.Type: GrantFiled: January 31, 2012Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Sung Park, Se-Myeong Jang, Gil-Sub Kim
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Patent number: 8633565Abstract: A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.Type: GrantFiled: July 21, 2010Date of Patent: January 21, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Ju Song, Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim
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Patent number: 8435840Abstract: A structure included in a semiconductor device can include a fuse box guard ring that defines an interior region of the fuse box inside the fuse box guard ring and that defines an exterior region of the fuse box outside the fuse box guard ring. The fuse box guard ring can include protruding support members that protruding from an interior sidewall or from an exterior sidewall of the fuse box guard ring.Type: GrantFiled: May 4, 2010Date of Patent: May 7, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Ho Kim, Gil-Sub Kim, Dong-Kwan Yang
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Publication number: 20120202336Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.Type: ApplicationFiled: January 31, 2012Publication date: August 9, 2012Inventors: Joo-Sung PARK, Se-Myeong Jang, Gil-Sub Kim
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Patent number: 8198664Abstract: A semiconductor memory device including a plurality of supports extending parallel to each other in a first direction on a semiconductor substrate, and capacitor lower electrode rows including a plurality of capacitor lower electrodes arranged in a line along the first direction between two adjacent supports from among the plurality of supports, each capacitor lower electrode including outside walls, wherein each of the capacitor lower electrodes includes two support contact surfaces on the outside walls of the capacitor lower electrode, the support contact surfaces respectively contacting the two adjacent supports from among the plurality of supports.Type: GrantFiled: October 28, 2009Date of Patent: June 12, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Gil-sub Kim
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Patent number: 8111501Abstract: A method of forming a capacitor includes forming a cylindrical lower electrode structure having an internal support structure on a substrate, forming a dielectric layer on the cylindrical lower electrode structure and the support structure, and forming an upper electrode on the dielectric layer.Type: GrantFiled: April 24, 2009Date of Patent: February 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Gil-Sub Kim
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Publication number: 20110298086Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.Type: ApplicationFiled: April 7, 2011Publication date: December 8, 2011Inventors: Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim, Ho-Ju Song
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Patent number: 8058678Abstract: Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.Type: GrantFiled: August 7, 2009Date of Patent: November 15, 2011Assignee: Samsunge Electronics Co., Ltd.Inventors: Gil-Sub Kim, Won-Mo Park, Seong-Ho Kim, Dong-Kwan Yang
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Patent number: 8043925Abstract: A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.Type: GrantFiled: November 6, 2009Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-kwan Yang, Seong-ho Kim, Won-mo Park, Gil-sub Kim
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Patent number: 8003464Abstract: Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.Type: GrantFiled: June 17, 2008Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Gil-sub Kim, Yong-il Kim, Jong-seop Lee, Jai-kyun Park, Yun-sung Lee, Nam-jung Kang
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Publication number: 20110049670Abstract: A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.Type: ApplicationFiled: July 21, 2010Publication date: March 3, 2011Inventors: Ho-Ju Song, Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim
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Publication number: 20100283117Abstract: A structure included in a semiconductor device can include a fuse box guard ring that defines an interior region of the fuse box inside the fuse box guard ring and that defines an exterior region of the fuse box outside the fuse box guard ring. The fuse box guard ring can include protruding support members that protruding from an interior sidewall or from an exterior sidewall of the fuse box guard ring.Type: ApplicationFiled: May 4, 2010Publication date: November 11, 2010Inventors: Seong-Ho KIM, Gil-Sub Kim, Dong-Kwan Yang
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Publication number: 20100237394Abstract: A semiconductor memory device includes unit active regions, word lines extending in a first direction over the unit active region, bit lines extending on the word lines in a second direction substantially perpendicularly to the first direction, first pad contacts in contact with central portions of the unit active regions, the first pad contacts being arranged between the word lines, direct contacts electrically connected between the first pad contacts and the bit lines, second pad contacts in contact with edge portions of the unit active regions, the second pad contacts being arranged between the word lines and between the bit lines, buried contacts electrically connected to the second pad contacts, and capacitors electrically connected to the buried contacts.Type: ApplicationFiled: March 19, 2010Publication date: September 23, 2010Inventors: Jai-Kyun Park, Hyeong-Sun Hong, Jong-Seop Lee, Yong-Il Kim, Yun-Sung Lee, Nam-Jung Kang, Jae-Hoon Song, Gil-Sub Kim
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Publication number: 20100200901Abstract: A semiconductor memory device including a plurality of supports extending parallel to each other in a first direction on a semiconductor substrate, and capacitor lower electrode rows including a plurality of capacitor lower electrodes arranged in a line along the first direction between two adjacent supports from among the plurality of supports, each capacitor lower electrode including outside walls, wherein each of the capacitor lower electrodes includes two support contact surfaces on the outside walls of the capacitor lower electrode, the support contact surfaces respectively contacting the two adjacent supports from among the plurality of supports.Type: ApplicationFiled: October 28, 2009Publication date: August 12, 2010Inventor: Gil-sub Kim
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Publication number: 20100187101Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, lower electrodes having cylindrical shapes are provided to be arranged repeatedly on a substrate. Upper surfaces of the lower electrodes are flat so that the lower electrodes have uniform heights. Supporting structures are provided between the lower electrodes to support the lower electrode, the supporting structure partially contacting outer surfaces of sidewalls of the lower electrodes that are arranged in a line. A dielectric layer is formed on surfaces of the lower electrodes and the supporting structures. An upper electrode is provided on the dielectric layer. The semiconductor device includes a capacitor having an improved capacitance. Further, the capacitor includes the support structure between the lower electrodes to prevent the adjacent lower electrodes from being short each other.Type: ApplicationFiled: January 22, 2010Publication date: July 29, 2010Inventors: Gil-Sub Kim, Won-Mo Park, Seong-Ho Kim, Dong-Kwan Yang, Ho-Ju Song
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Publication number: 20100187588Abstract: Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.Type: ApplicationFiled: August 7, 2009Publication date: July 29, 2010Inventors: Gil-Sub KIM, Won Mo PARK, Seong Ho KIM, Dong Kwan YANG
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Publication number: 20100120212Abstract: A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.Type: ApplicationFiled: November 6, 2009Publication date: May 13, 2010Inventors: Dong-kwan Yang, Seong-ho Kim, Won-mo Park, Gil-sub Kim
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Publication number: 20090268370Abstract: A method of forming a capacitor includes forming a cylindrical lower electrode structure having an internal support structure on a substrate, forming a dielectric layer on the cylindrical lower electrode structure and the support structure, and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: April 24, 2009Publication date: October 29, 2009Inventor: Gil-Sub Kim
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Publication number: 20090203204Abstract: Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.Type: ApplicationFiled: June 17, 2008Publication date: August 13, 2009Inventors: Gil-sub Kim, Yong-il Kim, Jong-seop Lee, Jai-kyun Park, Yun-sung Lee, Nam-jung Kang