Abstract: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a set of connection points among the circuit components at which the processing stage may be split for addition of multithreading capability to the circuit. A subset of the connection points is selected, and splitter components are inserted at the connection points in the subset.

Abstract: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit. The processing stage has inputs and outputs and includes circuit components arranged so as to define multiple logical paths between the inputs and the outputs. A timing constraint to be applied in splitting the processing stage into multiple sub-stages is specified. At least one of the logical paths is identified as a false path, to which the timing constraint is not to apply. The design is modified responsively to the timing analysis, to the timing constraint, and to identification of the false path, so as to split the processing stage into the sub-stages.

Abstract: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a set of connection points among the circuit components at which the processing stage may be split for addition of multithreading capability to the circuit. A subset of the connection points is selected, and splitter components are inserted at the connection points in the subset.

Abstract: A method for modifying a design of an original processor that is capable of running binary code with a given cycle-by-cycle execution pattern and includes an original pipeline having multiple phases. Each phase of the original pipeline is divided into at least two sub-phases, thereby providing a modified pipeline. Register sets and logic are coupled to the modified pipeline so as to create a multithreaded processor that is operative as a plurality of virtual processors, which have respective virtual pipelines supporting different, respective threads and which are able to run the same binary code as the original processor in each of the threads with the same cycle-by-cycle execution pattern as the original processor.

Abstract: A processor (100) capable of receiving a plurality of instructions sets from at least one memory (50), and capable of multi-threaded execution of the plurality of instruction sets. The processor includes at least one decoder (130) capable of decoding and interpreting instructions from the plurality of instruction sets. The processor also includes at least one mode indicator (140) capable of determining the active instruction-set mode, and changes modes of a software or hardware command and at least one execution unit (110) for concurrent processing of multiple threads, such that each thread can be from a different instruction set, and such that the processor processes the instructions according to the active instruction-set, which is determined by the mode indicator (140), and by allowing concurrent execution of several threads of several instruction sets.

Abstract: A method for indexing a plurality of ordered elements stored in bit-reversed order in a first and a second memory space, the first memory space indexed by a first memory index denoting memory positions in the first memory space, the second memory space indexed by a second memory index denoting memory positions in the second memory space, the logical position of the elements within the ordered elements indexed by an element index, the method including bit-reversing the element index of a selected element, locating the selected element as being in the first memory space where the MSB of the bit-reversed index equals 0 and the second memory space where the MSB of the bit-reversed index equals 1, and locating the position of the selected element within the MSB-located memory space at the memory index of the MSB-located memory space that corresponds to the non-MSB bits of the bit-reversed index.

Abstract: A method for in-place memory management in a Digital Signal Processing (DSP) architecture performing a Fast Fourier Transformation (FFT) upon a sequence of N data points, the sequence numbered from 0 to N-1, the method including storing each of the data points numbered from 0 to (N/2)-1 in a first memory space X and each of the data points numbered N/2 to N-1 in a second memory space Y, for each FFT stage 0 data point grouping including a first data point of the data points in the first memory space X and a corresponding second data point of the data points in the second memory space Y determining the parity of a data point memory index corresponding to the first and second data points, storing, if the parity is of a first parity value, the results of an FFT operation upon the first data point at the memory address in the first memory space X from which the first data point was fetched and the result of an FFT operation upon the second data point at the memory address in the second memory space Y from which t

Abstract: A method for advancing pointers in a memory including a sequence of N data points of a stage M of a Fast Fourier Transform (FFT) whose first stage is stage 0, the N data points including N/2 a data points and N/2 B data points, the N data points are stored in the memory in 2M groupings of a data points, each of the groupings having 2(Log2N)−1−M data points, and each of the groupings is followed by a grouping of 2(Log2N)−1−M B data points, the method including the steps of a) setting a pointer index Ap equal to the binary value of the data point memory index corresponding to the first A data point in the memory, b) setting a pointer index Bp equal to the binary value of the data point memory index corresponding to the first B data point in the memory, c) setting a first binary bit mask value R1 equal to 2(Log2N)−1−M+1, d) setting a second binary bit mask value R2 equal to 2(Log2N)−1−M, e) advancing the Bp pointer index to the data point memory index correspo

Abstract: A digital signal processor (DSP) including two multipliers and two three-input arithmetic logic units is able to perform a sequence of Fast Fourier Transform butterfly calculations such that results of a butterfly calculation in said sequence are available two cycles after results of an immediately previous butterfly calculation in said sequence are available.

Abstract: A digital signal processor (DSP) includes at least two multipliers, at least two three-input arithmetic logic units (ALU), at least two first-cycle registers, at least two second-cycle registers, and multiplexing apparatus. The digital signal processor is able to perform a Fast Fourier Transform (FFT) calculation in two consecutive processing cycles.

Abstract: A method is provided for converting a computer processor configuration having a k-phased pipeline into a virtual multithreaded processor, including dividing each pipeline phase of the processor configuration into a plurality n of sub-phases, and creating at least one virtual pipeline within the pipeline, the virtual pipeline including k sub-phases.

Abstract: A method for indexing a plurality of ordered elements stored in bit-reversed order in a first and a second memory space, the first memory space indexed by a first memory index denoting memory positions in the first memory space, the second memory space indexed by a second memory index denoting memory positions in the second memory space, the logical position of the elements within the ordered elements indexed by an element index, the method including bit-reversing the element index of a selected element, locating the selected element as being in the first memory space where the MSB of the bit-reversed index equals 0 and the second memory space where the MSB of the bit-reversed index equals 1, and locating the position of the selected element within the MSB-located memory space at the memory index of the MSB-located memory space that corresponds to the non-MSB bits of the bit-reversed index.

Abstract: An apparatus which generates even addressed words and odd addressed words in a memory. The apparatus consists of a port adapted for receiving an address, one or more even units in operative communication with the port and one or more odd units in operative communication with the port. The even units output an even address and the odd units output and odd address. If the input address is even the even address is equal to the input address and if the input address is odd the even address is spaced from the input address by N addresses, where N is an odd integer. If the input address is odd, the odd address is equal to the input address and if the input address is even, the odd address is spaced from the input address by N addresses.

Abstract: A device for performing a search for the optimum code vector in a codebook having N code vectors indexed by i has a controller which considers each ith code vector, and a processor which determines in two clock cycles whether said ith code vector is the current optimal code vector.