Abstract: A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank. In one arrangement, the controller controls the refresh operation to be selectively performed for a first rank in each of the memory chips during the non-overlapping time periods independently from a refresh operation performed for a second rank in each memory chip. Delay circuits or other logic may be included to ensure that the refresh operations do not overlap.