Abstract: Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data. The set of data includes multiple data bits. The first error correction code was generated using a generator matrix having multiple bit groups, each bit group including a unique set of bit positions. The integrated circuit also includes an error correction code generator operative to generate, using the generator matrix, a second error correction code that corresponds to the set of data. The integrated circuit further includes a comparator operative to generate a comparison result of the first error correction code and the second error correction code. The integrated circuit includes a data corrector operative to correct two consecutive data bits of the set of data.

Abstract: An embedded agent (104) of an integrated circuit (102) includes a collector (220) configured to receive from a tested target circuit a plurality of single bit lines of signals and a signal canceller (322) configured to receive an indication of lines that are not to be exported, for a given time period, and to set the indicated lines to a constant value. A linear combination calculation circuit (402) configured to generate a plurality of different linear combinations of the values of the single bit lines, for the clock cycles of the given time period, is also included in the embedded agent. A transmitter (216) exports from the chip a sub-group of the linear combinations calculated by the linear combination calculation circuit for the clock cycles of the given time period, the sub-group including a number of linear combinations selected responsively to the number of lines set to a constant value.

Abstract: A method of connecting to an integrated circuit. A target integrated circuit (102) is provided with an embedded agent (104) for exporting signals. While the target integrated circuit (102) is operating, data signals from one or more collection points (252) in the integrated circuit (102) are collected by the embedded agent (104), at least at a clock rate of operation of the integrated circuit at the one or more collection points (252), in parallel to the target circuit (102) operation. The collected data signals are inserted into packets, by the embedded agent (104) and the packets are transmitted to a unit external to the integrated circuit, in real time.

Abstract: System for generating and managing communication accomplished by means of graphical layers is provided. The graphical layers may comprise graphical features, text pictures and computerized objects such as media player for displaying a selected film, The system enables a user to call one or more of her or his colleagues to on-line collaborate in consideration with a selected content. The system provides a user for generating a new graphical layer, adding or deleting user generated content (UGC) into, or off a graphical layer generated by another user. The system stores completed graphical layers in a database. The system successively combines graphical layers associated to the same selected content into a track, which is further stored in the database. The system provides a user for tracking a selected user who so permitted while selected user is wondering and searching the World Wide Web.

Abstract: A speech reconstruction method and system for converting a series of binned spectra or functions thereof such as the Mel Frequency Cepstra Coefficients (MFCC), of an original digitized speech signal, into a reconstructed speech signal, where each binned spectrum has a respective pitch value and voicing decision. The binned spectra are derived from the original digitized speech signal at successive instances by multiplying each estimate of the spectral envelope by a predetermined set of frequency domain window functions and computing the integrals thereof. At each respective time instance, harmonic frequencies and weights are generated according to the respective pitch value and voicing decision. Basis functions having bounded supports on the frequency axis are each sampled at all said harmonic frequencies, which are within its support and multiplied by respective harmonic weights.

Abstract: Apparatus is described for digitally encoding an input audio signal for storage or transmission. A distinguishing parameter is measure from the input signal. It is determined from the measured distinguishing parameter whether the input signal contains an audio signal of a first type or a second type. First and second coders are provided for digitally encoding the input signal using first and second coding methods respectively and a switching arrangement directs, at any particular time, the generation of an output signal by encoding the input signal using either the first or second coders according to whether the input signal contains an audio signal of the first type or the second type at that time. A method for adaptively switching between transform audio coder and CELP coder, is presented. In a preferred embodiment, the method makes use of the superior performance of CELP coders for speech signal coding, while enjoying the benefits of transform coder for other audio signals.

Abstract: Apparatus is disclosed for digitally encoding an input audio signal, for storage or transmission, comprising: a pitch detector for determining at least a dominant time-domain periodicity in the input signal; a generator for generating a prediction signal based on the dominant time domain periodicity of the input signal; a first discrete frequency domain transform generator for generating a frequency domain representation of the input signal; a second discrete frequency domain transform generator for generating a frequency domain representation of the prediction signal; a subtractor to subtract at least a portion of the frequency domain representation of the prediction signal from the frequency domain representation of the input signal to generate an error signal; and a generator to generate an output signal from the error signal and parameters defining the prediction signal. A corresponding decoder is also described.